We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms were developed based on a single local optimization function, called the sequential cut line objective function. Our algorithm incorporates global objective functions into this traditional framework of min-cut placement. In particular, we introduce a new global objective function based on the congestions for cut lines and use it for the selection of their sequence. We also use the total cut value objective function in the determination of the sizes and connectivities of clusters that are to be used in the early stages of min-cut partitioning. The incorporation of such global objective functions yields additional reductions of wire congestions in the entire as well as local chip areas. With the automatic selection and use of such clusters and a cut line sequence, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. This has led to its successful production use, having generated more than 400 CMOS sea-of-gates array chips of 1.5 K to 150 K raw gates.>

We introduce a new model for over-the-cell channel routing with three layers. The model consists of two channels and the routing area over a cell row between them. Three and two layers are available for routing in the channels and the over-the-cell routing area, respectively. We formulate the problem of over-the-cell routing as that of channel routing with additional constraints. Based on this formulation, we present an efficient over-the-cell routing algorithm that attempts to minimize the sum of channel densities of the trunks that remain in the channel. The effectiveness of our model and algorithm is demonstrated by our experimental results on industrial sea-of-gates array chips and a well-known benchmark circuit.>

The authors propose an approach to an over-the-cell channel routing problem using a model that consists of two channels and the routing area over a cell row between them. Three and two layers are available for routing in the channels and the over-the-cell routing area, respectively, The problem is decomposed into two phases: over-the-cell routing and channel routing. The authors formulate the problem in the first phase as that of channel routing with additional constraints. Based on this formulation, they present an efficient over-the-cell routing algorithm. The effectiveness of the approach is demonstrated by experimental results on sea-of-gates array chips.>

This paper presents a new min-cut placement algorithm for timing assurance layout design. When critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. This algorithm is built into the layout system for gate arrays called GALOP [1] and has been successfully applied to clock skew control of an ECL 12K-gate gate array.

This paper provides an outline, together with application results and functional improvements, of the symbolic layout system MGX. MGX was developed to support the layout design of the functional blocks of microprocessors for MOS technology. The point considered the most important when we started developing MGX is reducing design time without much waste of silicon area. In order to achieve this goal, a layout style in MGX in which all symbolic layout elements are on movable grid points and which has an orderly structure is adopted, and the fast compaction algorithm is selected. Another consideration for the system is to support the whole LSI layout process. Using MGX, a 16-bit microcontroller chip was successfully designed. MGX offered high transistor packing density and high productivity of the layout design. The experience with this layout design has shown that another goal to be achieved in the development of a symbolic layout system is the ability to update designed physical layout patterns with advances in LSI fabrication technology without having to redo the layout. Hence, MGX has been improved so as to deal with various design rules which may become possible with advances in LSI fabrication technology and to give higher transistor packing density. Experimental results show that the transistor packing density of the layout of a D flip-flop which is designed by using MGX increases by approximately 39 percent due to these improvements.

The channel router, which routes a rectangular channel with two rows of terminals along its top and bottom sides, is extensively used for the automatic routing of gate arrays. It is well known that in this routing method the routing can not be performed when the vertical constraint graph contains cycles. This paper deals with the problem of eliminating cycles in the vertical constraint graph by interchanging the nets assigned to logically equivalent terminals before channel routing. A heuristic algorithm is proposed for this problem. This algorithm yields a locally optimum assignment of nets to terminals, in the sense that the number of independent cycles in the vertical constraint graph of a resultant assignment can not be reduced by interchanging any pair of the nets assigned to logically equivalent terminals. Furthermore, in order to speed up the operation of this algorithm, it is shown that the checking as to whether or not the number of independent cycles in the vertical constraint graph is reduced can be done by noting only its subgraph, when a pair of nets assigned to logically equivalent terminals are interchanged. Experimental results have indicated that this proposed algorithm is efficient.

In the masterslice LSI, since the wiring area is fixed, local wiring congestion is likely to occur, which may cause the occurrence of some wiring nets to be unroutable. If the number of grids used in the routing can be accurately predicted before the wire routing, it is possible to reduce greatly the occurrence of wiring nets to be unroutable.