Quantum-dot Cellular Automata is an emerging technology that offers significant improvements over CMOS. Recently QCA has been advocated as a technology for implementing reversible computing. However, existing tools for QCA design and evaluation have limited capabilities. This paper presents a new mechanical-based model for computing in QCA. By avoiding a full quantum-thermodynamical calculation, it offers a classical view of the principles of QCA operation and can be used in evaluating energy dissipation for reversible computing. The proposed model is mechanically based and is applicable to six-dot (neutrally charged) QCA cells for molecular implementation. The mechanical model consists of a sleeve of changing shape; four electrically charged balls are connected by a stick that rotates around an axle in the sleeve. The sleeve acts as a clocking unit, while the angular position of the stick within the changing shape of the sleeve, identifies the phase for quasi-adiabatic switching. A thermodynamic analysis of the proposed model is presented. The behaviors of various QCA basic devices and circuits are analyzed using the proposed model. It is shown that the proposed model is capable of evaluating the energy consumption for reversible computing at device and circuit levels for molecular QCA implementation. As applicable to QCA, two clocking schemes are also analyzed for energy dissipation and performance (in terms of number of clocking zones).

This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Jitter is analyzed by considering separate and combined components. The primary goal is the generation of a signal containing a known amount of each jitter component. This signal can then be used for testing high speed serial data channels. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining them are modeled, simulated and evaluated. Model simulation using Matlab is utilized to show the unique features of the components when they are combined into different injection sequences for producing the total jitter. Sequence dependency is investigated in depth and the validity of superposition of jitter components for typical values is confirmed. A good agreement between theory and simulation is verified; these results allow test engineers to have an insight into the interactions among jitter components in serial data channels.

Self-assembly by DNA tiles has been advocated as a possible technique for bottom-up manufacturing of scaffolds in the nanoscale region. However, self-assembly is severely affected by facet roughening errors. A particularly effective error tolerant method utilizes snake tile sets with a square block of even dimension (i.e. 2 k times 2 k) of tiles. Snake tile sets of odd dimension (i.e. (2 k - 1) x (2k - 1)) have also been proposed. To analyze error tolerant mechanism of snake tile sets, this paper presents an analytical Markov model for facet roughening errors. A generalized model is proposed and used to analyze snake tile sets for the realistic cases of k = 2 and 3. Closed form solutions are attained in the analysis. Simulation results are presented to confirm that snake tile sets of odd dimension are more tolerant to facet errors than other tile sets for self-assembly.

As a possible technology for bottom-up manufacturing, DNA self-assembly requires tolerance to different errors. Among the methods for reducing the error rate, snake tile sets utilize a square block of even dimension of tiles (i.e., 2ktimes2k). In this paper, an odd-sized square block (i.e., (2k-1)times(2k-1)) is proposed as basis for snake tile sets. In comparison with all other tile sets, the proposed snake tile sets achieve a considerable reduction in error rate for growth and facet roughening errors. Simulation results are provided.

Quantum dot Cellular Automata (QCA) is one of the promising technologies for nano scale implementation. The operation of QCA systems is based on a new paradigm generally referred to as processing-by-wire (PBW). This paper analyzes the defect tolerance properties of PBW when tiles are employed using molecular QCA cells. Based on a 3×3 QCA block, with different input/output arrangements, different tiles are analyzed and simulated using a coherence vector engine. The functional characterization and polarization level of these tiles for undeposited cell defects are reported. It is shown that novel features of PBW are possible due to spatial redundancy and QCA tiles are robust and inherently defect tolerant.

The design of circuits and systems in Quantum-dot Cellular Automata (QCA) is still in infancy. The basic logic primitive in QCA is the majority voter (MV), that is not a universal function; so, inverters (INV) are also required. Blocks (referred to as tiles) are utilized in this article. A tile with a combined logic function of MV and INV (MV-like function) is proposed. It is shown that the MV-like tile can be effectively used in logic design as basic primitive. Tiles based on both the fully populated (FP) and non-fully populated (NFP) grids are investigated in detail. Various arrangements in inputs and outputs are also possible among the 4 sides of a grid, thus defining different tiles. Using a coherence vector simulation engine, it is shown that the 3 × 3 grid offers versatile logic operation. Different combinational functions such as majority-like and wire crossing are obtained using these tiles. Tile-based design of different circuits is compared to gate-based and SQUARES designs.

Quantum-dot cellular automata (QCA) offers a new computing paradigm for nanotechnology. The basic logic elements of this technology are the majority voter (MV) and the inverter (INV). However, an experimental evaluation has shown that MV is not efficiently used during technology mapping by existing logic-synthesis tools. In this paper, we propose the design and characterization of a novel complex, yet very small, QCA logic gate: the and-or-inverter (AOI) gate. The paper presents a detailed simulation-based analysis of the AOI gate, as well as the study of QCA defects and their effects at the logic level. The AOI implements a universal logic gate; all elementary gates can be implemented by the AOI gate. Moreover, many two-level logic functions can be directly implemented by a single AOI gate. The AOI gate performs quite favorably, in terms of digital logic synthesis. Unlike MV, this gate is efficiently used by existing logic-synthesis tools. Our experimental data on synthesis of complex designs show that using the AOI gate instead of MV, results in up to 23.9% logic area savings, while improving the overall delay.

A new application-independent approach for evaluating the fault tolerance of field-programmable gate-array (FPGA) interconnect structures is presented. Signal routing in the presence of faulty resources at switch block and FPGA levels is analyzed; this problem is directly related to the fault tolerance of FPGA interconnects for testing and reconfiguration at manufacturing and run-time applications. Two criteria are proposed and used as figure-of-merit for evaluating different FPGA interconnect architectures. The proposed approach is based on the number of available paths between pairs of end points and the probability to establish a one-to-one mapping between all input and output end points. A probabilistic approach is also presented to evaluate the fault-tolerant routing of the entire FPGA by connecting switch blocks in chains, as required for testing and to account for the input-output (I/O) pin restrictions of an FPGA chip. All possible interconnect faults for programmable switches and wiring channels are considered in the fault model. The proposed method is applicable to arbitrary switch block structures. Experimental results on commercial as well as academic designed FPGAs are presented and analyzed.

This paper presents a new approach for the evaluation of FPGA routing resources in the presence of faulty switches. This is considered under the worst case scenario of open faults. Signal routing in the presence of faulty switches is analyzed at switch block level; probabilistic routing (routability) is used as figure of merit for evaluating the interconnect resources of FP-GAs. The presented approach utilizes a path-based technique to find the probability of establishing a path between pairs of input and output endpoints in a switch block. The results are reported for various commercial and academic FPGAs.

Quantum-dot Cellular Automata (QCA) offers a new computing paradigm in nanotechnology. The basic logic elements of this technology are the inverter and the majority voter. In this paper, we propose a novel complex and universal QCA gate: the And-Or-Inverter (AOI) gate, which is a 5 input gate consisting of 7 cells. This paper presents a detailed simulation-based analysis of the AOI gate as well as the characterization of QCA defects and study of their effects at logic level. Design implementations using the AOI gate are compared with the conventional CMOS and the majority voter-based QCA methodology. Testing of the AOI gate at logic level is also addressed, unique testing features of designs based on this complex gate have been investigated.

Summary form only given. We present a new approach for the evaluation of FPGA routing resources in the presence of faulty switches. Switch stuck-open faults (switch permanently off) as well as switch stuck-closed faults (switch permanently on) are addressed, which is directly related to fault tolerance of the interconnect for testing and reconfiguration at manufacturing and run-time application. Signal routing in the presence of faulty switches is analyzed at both switch block and array levels; probabilistic routing (mutability) is used as figure of merit for evaluating the programmable interconnect resources of FPGA architectures. Two approaches are proposed in this paper. The first approach is based on finding a permutation (one-to-one mapping) between the input and output endpoints. A probabilistic approach is also presented to evaluate fault tolerant routing for the entire FPGA by connecting switch blocks in chains as required for testing and to account for the I/O pin restrictions of an FPGA chip. The results are reported for various commercial and academic FPGA architectures.

Summary form only given. There has been considerable research on quantum cellular automata (QCA) as a new computing scheme in the nanoscale regimes. A detailed simulation-based characterization of defects in different QCA logic and interconnect devices and study of their effects at logic-level are presented. Various failure mechanisms which can potentially happen during nanomannfacturing of these devices have been considered and simulated. Different implementations of QCA logic devices and interconnects are also compared in term of defect tolerance and testability. The same study is performed for new proposed QCA devices too. The simulation results show that additional fault models at logic level must be considered for testing of QCA-based circuits.

This work presents a new approach for the evaluation of FPGA routing resources in the presence of interconnect faults. All possible interconnect faults for programmable switches and wiring channels are considered. Signal routing in the presence of faulty interconnect resources is analyzed at both switch block and the entire FPGA. Two new probabilistic routing (routability) metrics are proposed and used as figures of merit for evaluating the interconnect resources of commercially available FPGAs as well as academic architectures.

There has been considerable research on quantum dot cellular automata (QCA) as a new computing scheme in the nano-scale regimes. The basic logic element of this technology is majority voter. In this paper, a detailed simulation-based characterization of QCA defects and study of their effects at logic-level are presented. Testing of these devices is investigated and compared with conventional CMOS-based designs. Unique testing features of designs based on this technology are presented and interesting properties have been identified.