The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in$\mathbf{33D}$stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1)$\mathbf{100x}$performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2)$\mathbf{50x}$processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm2.

This IP session will consist of three presentations. A summary of each presentation is given below.

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1-$\mathrm {W}/{\mathrm {mm}}^{2}$power-density target for high-performance computing (HPC) systems, a 25-high-$Q$-factor (300 MHz), 150-$\mu \text{m}$-thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57-$\mu \text{m} V_{\mathrm {DD}}$-bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10-$\mu \text{m}$-horizontal-pitch nano- through-silicon via ($n$TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency$\eta \,\,=83$% can be obtained for 1-$\mathrm {W}/{\mathrm {mm}}^{2}$power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.

We present a$\mu \text{m}$-thin-profile power delivery solution including a charge pump with integrated passives. Targeting 1 W/mm2or higher power density, a 2.5-D high-density metal-insulator-metal (MIM) capacitor deposited on high aspect ratio (HAR) (up to 5) oxide studs is proposed. With approximately 25-nm-thick HfAlOx dielectric, its measured capacitance density is 25.4 nF/mm2for a capacitor size ranging from 1/16 mm2to 1 mm2. This shows$3.6\times $density improvement compared with the planar MIM. Theoretically, 86 nF/[email protected] bias can be obtained if a 10-nm dielectric is deposited. Moreover, the measured leakage current density is within 65 pA/mm2at 1-V bias (negligible for a 1 W/mm2-power delivery). For a backside (BS) power delivery, this 2.5-D MIM capacitor can be realized by only three BS metal layers. This enables the low-cost and thin-profile delivery system ($\sim \!\!\mu \text{m}$thickness), and the whole power delivery efficiency including a 1/2-ratio charge pump is$\eta \,\,=84$%@1 W/mm2(>5% boost in the power efficiency).

Efficient processing of fine-pitched Through Silicon Vias, micro-bumps and back-side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows typically conceived for 2D systems. With all system, technology and implementation level options brought with these features, the design space increases to an extent where traditional 2D tools cannot be used any more for efficient exploration. Therefore, the cost-effective design of future 3D ICs products will require new planning and co-optimisation techniques and tools that are fast and accurate enough to cope with these challenges. In this paper we present design methodology and the practical EDA tool chain that covers different aspects of the design flow and is specific to efficient design of 3D-ICs. Flow features include: fast synthesis and 3D design partitioning at gate level, TSV/micro-bump array planning, 3D floor planning, placement and routing, congestion analysis, fast thermal and mechanical modeling, easy technology vs. implementation trade-off analysis, 3D device models generations and Design-for-Test (DfT). The application of the tool chain is illustrated using concrete example of a real-world design, showing not only the applicability of the tool chain, but also the benefits of heterogeneous 2.5 and 3D integration technologies.

Three dimensional integration complements semiconductor scaling; it enables a higher integration density as well as heterogeneous technology integration. Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realized using advanced CMOS technology nodes but may also exploit a wide variety of device technologies to optimize system performance.

We present a compact model that provides a quick estimation of the stress and mobility patterns around arbitrary configurations of Through-Silicon Via's (TSVs). No separate TCAD simulations are required for these configurations. It estimates nFET and pFET mobility for industry-standard as well as for (100)/substrate orientations. As the model provides mobility info in less than 0.1 millisecond/transistor/TSV, it is possible to be used in combination with layouting tools and circuit simulators to optimise layouts of circuits for digital and analog applications. The model has been integrated into the 3D PathFinding flow, for steering 3D IO placement during stack definition.

It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moore's law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies.

Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission lines in power grids. The transmission lines are well suited for high quality intra-chip signal transmission at multi gigabit data rates. By having signal lines between the power grids, the VDD and GND lines in the grid can be exploited as return paths besides being used for regular power distribution. This approach also improves wiring density. In this paper, we rigorously analyze and discuss the design considerations for laying transmission lines in power grids. We also present design oriented modeling methods in 2D and 3D geometry. We show how the grid modeling complexity is simplified. We experimentally validate our results with fabricated test structures. We also show VDD lines in the grid act as good return path without external decoupling capacitors in our design. Further we discuss substrate effects and deduce guidelines for designing power grid transmission lines on a low resistive silicon substrate

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a a common carrier onto which different ICs are mounted. passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The "system-on-a-package" approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications.

This paper describes the analysis of the propagation of digital signal on a thin-film multichip module (MCM) substrate populated with CMOS integrated circuits. Timing analyses and circuit simulations were performed during the design of an MCM consisting of 4 bare 0.7-/spl mu/m CMOS ASIC's (100 pins, 64 mm/sup 2/, standard cell technology) transmitting signals at 200 Mbit/s on a 5-layer thin-film substrate (1-by-1 inch, 2 interconnection layers). This paper addresses mainly two problems related to the design of microsystems where trade-offs must be found between high frequency and high density requirements: 1) an accurate description of the chip-to-chip, propagation of the signals, including the combined influence of active devices (drivers and receivers) and coupled, lossy interconnection lines: 2) an accurate overview of the way parameters from different domains (geometrical, electrical and technological) interact with each other and affect together the signal propagation. It is shown how the results of such analyses can help solving trade-offs between different requirements and taking decisions during the system design phase.