In this paper, an output-dependent delay cancellation (ODDC) technique is proposed. For a high-accuracy digital-to-analog converter (DAC), the delay differences caused by output voltage is one of the major nonlinearities that deteriorate the dynamic performance. The ODDC technique has the advantages of significant improvement on the dynamic performance in a wide frequency range without increasing the noise floor. ODDC can eliminate the switching time variations caused by output voltage of DAC through tuning the bulk voltage of switches in the deep N-well. The algorithm of ODDC technique is derived. To verify the implementation, a 14 bits 400MS/s current-steering DAC with ODDC is simulated and the SFDR can be improved by about 12dB with proper circuit parameters.

The automatic frequency calibration (AFC) technique is routinely used in the wideband frequency synthesizers which contain multiple voltage-controlled oscillator (VCO) tuning curves. In this paper, a counter-based AFC design method is presented. The relationship between the AFC counting time and the VCO tuning curve characteristic is quantitatively analyzed. An AFC circuit which uses a time-to-digital converter (TDC) in the counting process is developed. Simulation results show that the proposed circuit significantly reduces the AFC calibration time while preserving the calibration accuracy. The simulated error-free AFC time of the proposed AFC is less than 3 µs.

A CMOS 80-400 MHz 5THorder Chebyshev Gm-C low-pass filter with a unique auto tuning system is presented. The filter was designed and fabricated with TSMC 0.13-μm RF CMOS process. Experimental results show that the cut-off frequency of the filter can be tuned between 80-400 MHz, with a tuning step less than 7MHz and an average tuning error of 3.6%. The filter also realizes gain of 0-30 dB, IIP3 of 16.5 dBm and NF of 14-18 dB. Dynamic range of the filter for THD less than 1% is 74 dB. Power dissipation is only 9 mW with 1.2 V supply voltage.

A Nyquist-rate time-interleaved current-steering digital-to-analog converter (DAC) with dynamic channel matching (DCM) is proposed. Thanks to the proposed Nyquist- rate time-interleaved architecture, the DAC can properly operate at more than lGS/s for a near-Nyquist output signal. The key limitation of the time-interleaved architecture is the mismatches between channels. The proposed DCM method can be applied to significantly suppress the spurious tones caused by imperfect channel matching. A 14-bit 1 GS/s current-steering DAC with behavior models and a 0.18μm CMOS technology is simulated to illustrate the wideband time-interleaved architecture and the harmonic elimination of the DCM.

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13 μm CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is -123 dBc/Hz at 1 MHz offset from a 1.8 GHz carrier. The spectral purity is better than 45 dBc from the output of mixer. The locking time of PLL is about 40 μs with an AFC time less than lOμs. The 0.4-6 GHz synthesizer consumes only 35 mW to 51 mW from a 1.2 V supply.

This paper presents the design of a sideband-suppressed synthesizer for dual-carrier MB-OFDM transceivers covering 11 frequency bands from 6.2GHz to 9.4GHz and 3 frequency bands from 4.2GHz to 4.8GHz, each with a bandwidth of 264MHz. Careful band plan is made to minimize the complexity. The synthesizer generates 14 carrier frequencies from a single frequency source. Improvements are made to the circuits to further suppress the sidebands. The synthesizer chip is designed with TSMC's 0.13-μm RF CMOS technology. The circuit draws a current of 42mA from a 1.2V supply. It achieves a sideband rejection of 45dBc and a phase noise of -105dBc/Hz@1MHz.

This paper presents a current-mode 6~9GHz RF transmitter for OFDM-UWB system applications. By a current-mode low pass filter with variable gain between the digital-to-analog converter and the up-conversion mixer, this transmitter exceeds the traditional voltage-mode counterpart in terms of high linearity (+3.5-dBm output 1-dB compression point, +12.5-dBm output third intercept point) and low spurious emission (50-dB sideband rejection) with low power consumption (40-mA current under 1.2-V supply voltage). By an output power flattening technique, the output power ripple is restricted within ±0.5dB. By an inductor-less divider and active-inductor LO buffer, a small die area of 0.72 mm2is obtained with TSMC's 0.13-μm 1P8M RF CMOS technology. The design is verified through post-layout simulations.

This paper presents a Sigma-Delta fractional-N frequency synthesizer for multi-standard receiver. The synthesizer's output range is 1.8~5.8GHz and covers the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802. Ha/b/g and Bluetooth. Frequency planning is elaborately done to make sure the synthesizer meets specifications of standards mentioned above. QVCO with a proposed phase shifter is shown to have better phase noise performance and more stable oscillation. Simulated phase noise is -119dBc/Hz at 1-MHz offset from a 4.2GHz carrier. Its FOM ranges from 181 to 187. The frequency synthesizer is fabricated in TSMC 0.13um CMOS process. Average power consumption is 55.92mW.

This paper presents a 10-bit 40-MS/s pipelined ADC in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB SFDR and 57.3 dB SNDR within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a FOM value of 0.22 pJ/step.

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters to create the class-AB behavior in the first and second stages. With this structure, the transconductances (gm) of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode Miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results present the sample-and-hold (S/H) of the 11-bit 40-MHz pipelined ADC using the proposed amplifier consumes only 5.5 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio(SNDR) 78.78 dB, spurious-free dynamic range (SFDR) 87.2 dB and total harmonic distortion (THD) -85.9 dB with 19.1 MHz full-swing input signal.

This paper presents a power-optimized quadrature VCO with wide-tuning range for UWB Receivers. The optimization of power is achieved by both optimum selection of LC tand and the improvement of the conventional VCO. To increase the tuning range, the digital controlled capacitor array is exploited. The circuitry is implemented by the 0.18um RF/mixed signal process. The proposed VCO achieves phase noise of 125dBc/Hz at 1-MHz offset and 34% tuning range while consuming 3.5mA in 1.6-V supply. Figure-of-merit with tuning range of the proposed VCO is which is the lowest among the recent state-of-the-art low-voltage VCOs.