In modern package design, the flip-chip package has become mainstream because of the benefit of its high I/O pins. However, the package design is still done manually in the industry. The lack of automation tools makes the package design cycle longer due to complex routing constraints, and the frequent modification requests. In this work, we propose yet another routing framework for substrate routing. Compared with previous works, our routing algorithm generates a feasible routing solution in a few seconds for industrial design and considers important symmetry and shielding constraints that have not been handled before. Benefiting from the efficiency of our routing algorithm, the designer can get the result immediately and accommodate some modifications to reduce the cost. The experimental result shows that the routing result generated from our router is in good quality, very close to the manual design.

Capacitance-ratio mismatch in a switched-capacitor circuit could significantly degrade circuit performance. In the nanometer era, the parasitic effects and lengths of interconnects both have significant impacts on the capacitance ratio. This paper presents the first routing work for the problem of coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. The router adopts a two-stage approach of topology generation followed by detailed routing to route unit capacitors such that the coupling-aware wire length ratio can match the desired capacitance ratio. Given a length ratio, in particular, the length-ratio-matching routing problem can be handled by transforming the problem into an easier classical wirelength minimization one. Experimental results show that our algorithm can solve the addressed problem with substantially smaller costs.

Asynchronous circuits are a promising design style for low-power and high-performance applications, where asynchronous templates have been widely used to automate the design of asynchronous circuits to reduce design efforts such as the implementation of handshaking mechanisms. Among the templates, pipeline templates are popular in high-performance systems. This paper presents an asynchronous template that can generate pipelines with low glitch-power consumption under the two-phase bundled-data protocol. Moreover, operations of our pipeline template can be hazard-free by simple techniques. We further analyze the timing constraints of pipelines based on the template, and then introduce two practical extensions of using the template. Compared with the prior work considering glitch-power reduction, pipelines using our proposed template can achieve significantly higher performance, lower power consumption, and less area overhead, with similar glitch-power reduction.

Capacitance-ratio mismatch in a switched-capacitor circuit could significantly degrade circuit performance. In the nanometer era, the parasitic effects and lengths of interconnects both have significant impacts on the capacitance ratio. This paper presents the first routing work for the problem of coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. The router adopts a two-stage approach of topology generation followed by detailed routing to route unit capacitors such that the coupling-aware wire length ratio can match the desired capacitance ratio. Given a length ratio, in particular, the length-ratio-matching routing problem can be handled by transforming the problem into an easier classical wirelength minimization one. Experimental results show that our algorithm can solve the addressed problem with substantially smaller costs.

With increasing circuit complexities, design bugs are commonly found in late design stages, and thus engineering change orders (ECOs) have become an indispensable process in modern VLSI design. Most prior approaches to the timing ECO problem are concerned about combinational logic optimization. In contrast, this paper addresses the problem in the sequential domain to explore more optimization flexibility. We propose an orthogonal method of post-mask clock scheduling with spare cells. Compared to traditional clock scheduling, clock scheduling in the ECO stage is more challenging in that it confronts limited spare-cell resources and dynamic changes of wiring cost incurred by different spare-cell selections. Based on mixed-integer linear programming (MILP), our formulation considers not only gate sizing and buffer insertion using spare cells, but also wire snaking. Experimental results based on five industrial designs show the effectiveness of our work. Our framework has been integrated into a commercial design flow.

This paper presents the constraint of input and output design of a nonlinear system via sum of square (SOS). This proposed SOS-based controller is able to limit the closed-loop system to satisfy the input and output constraints. Those SOS constraint conditions are more general than the existing linear matrix inequality (LMI) constraint conditions. The constraint conditions are represented in terms of sum of squares of the polynomial fuzzy systems and can be numerically solved via the recent developed SOSTOOLS. To illustrate the validity of the constraint design approach with stability condition, a design example is provided. Computer simulations show that the SOS-based approaches are more effective than the LMI-based approaches.

Due to increasing integrated circuit design complexity, engineering change orders (ECOs) have become a necessary technique to resolve late-found functional errors and/or performance deficiencies. To fix timing violations, gate sizing and buffer insertion are commonly used in postmask ECO. These techniques, however, may not be powerful enough, especially when spare cells are inserted to balance between functional and timing repair capabilities. We propose a postmask ECO technique, called TRECO, to remedy timing violations based on technology remapping, which also supports functional ECO. Unlike conventional technology mapping, TRECO performs technology mapping with respect to a limited set of spare cells and confronts dynamic changes of wiring cost incurred by selection of different spare cells. With a precomputed lookup table of representative circuit templates, TRECO iteratively performs technology remapping to restructure timing critical subcircuits until no timing violation can be further removed. Experimental results on five industrial designs show the effectiveness of TRECO in ECO timing optimization and in timing-aware functional ECO.

Due to the increasing IC design complexity, Engineering Change Orders (ECOs) have become a necessary technique to resolve late-found functional and/or timing deficiencies. To fix timing violations, the principles of gate sizing and buffer insertion are commonly used in post-mask ECO. These techniques however may not be powerful enough, especially when spare cells are inserted in a way of striking a balance between functional and timing repair capabilities. We propose a post-mask ECO technique, called TRECO, to remedy timing violations based on technology remapping, which supports functional ECO as well. Unlike conventional technology mapping, TRECO performs technology mapping with respect to a limited set of spare cells and confronts dynamic changes of wiring cost incurred by different spare-cell selections. With a pre-computed lookup table of representative circuit templates, TRECO iteratively performs technology remapping to restructure timing critical sub-circuits until no timing violation remains. Experimental results on five industrial designs show the effectiveness of TRECO in ECO timing optimization.

For high-performance chip designs, a clock network with high tolerance towards process-variation is essential for chip synchronization. Clock mesh structure are widely used in these designs because of its resistant to variations. However, traditional mesh structures suffer from several drawbacks such as difficulty in timing estimation, inability to handle obstacles, and high power consumption. This paper proposes a new obstacle-avoiding clock mesh synthesis method which applies a two-stage approach of mesh construction followed by driving-tree synthesis. The method achieves very low skew through structural optimization, thus eliminating the need of direct timing estimation and/or SPICE simulation during clock network synthesis. In addition, our approach handles obstacles with the structural consideration, and reduces power consumption by removing non-critical mesh components and optimizing the driving-tree structure. Based on the benchmarks of the ISPD'10 Clock Network Synthesis Contest, the top contest performers result in 1.32X skew over our approach by using mesh structure, and more than 2.0X skew over our approach by using tree structure. Our approach runs 8326X/11421X faster than teams that used simulation, and 67X/90X times faster than teams that did not use simulation.

We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost: once a standard cell is placed, its physical location is fixed and so is its wiring cost. For the spare-cell rewiring problem, each rewiring could make some spare cells become ordinary standard cells and some standard cells become new spare cells simultaneously. As a result, the wiring cost becomes dynamic and further complicates the optimization process. For the addressed problem, we present a two-phase framework of 1) buffer insertion and gate sizing followed by 2) technology remapping. For Phase 1, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming, for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. For those ECO timing paths that cannot be fixed during Phase 1, we apply technology remapping on the spare cells to restructure the circuit to fix the timing violations. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.

In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this article, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the clock skews produced by three algorithms (Partition, MST, Matching) in the absence of post clock tuning steps in the previous work are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of the previous work in reducing peak current and power/ground noises.

Nanometer effects have complicated the designs of chips as well as packages and printed circuit boards (PCB’s). In order to improve the performance, convergence, and signal integrity of the design, chip-package-board co-design is strongly recommended by industry. In this paper, we present the first routing algorithm in the literature for chip-package-board co-design with differential-pair considerations. Our algorithm is based on linear programming and integer linear programming and guarantees to find an optimal solution for the addressed problem. It first creates global-routing paths among chips, packages, and a PCB. Without loss of the solution optimality, our routing formulation can reduce the numbers of integer variables (constraints) by 95% (99%) on average. Then, any-angle routing is applied to complete the routing. Experimental results based on five real industry designs show that our router can achieve 100% routability and the optimal global-routing wirelength and satisfy all differential-pair constraints, under reasonable CPU times, whereas recent related work results in much inferior solution quality.

In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this paper, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the dock skews produced by three algorithms (Partition. MST, Matching) [5] are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [5] in reducing peak current and power/ground noises.