In view of investigating new strategies to cope with the limitation of high output power of very high frequency power converters, this paper describes the implementation of Class E2 parallel resonant DC-DC converters which is suitable candidate topology for the experiment as it can maintain ZVS over a wide load range naturally in open-loop. Consequently, several 10W elementary prototypes were gathered which maintain an overall efficiency >80% for a load range variation of 2-10W at a switching frequency of 10MHz. Subsequently, multiple paralleling configurations are investigated experimentally which allowed the construction of a predictive model for untested parallel converter configurations. A maximum output power of 42.78W was achieved with 5 parallel converters..

This paper describes the ongoing research towards identifying a best candidate topology of Very High Frequency power converter with the goal of paralleling standard cells. Such an association of similar elementary converters requires load independence. A benchmarking highlights a Class E2 resonant DC-DC converter. The paper details the selection and identify equipment needs for testing the candidate topology as well as a parallel association.

Designing efficient, compact DC-DC converters for ultra-low power applications (below mW) is challenging, primarily due to significant switching losses. In contrast to switched-capacitor converters, switched-battery converters (SBCs) have recently emerged as a solution capable of maintaining high efficiency even at ultra-low frequencies (in the Hz range), while still achieving reasonable power density. However, initial SBC demonstrations relied on button cell batteries, which limited practical adoption in compact systems. This paper presents the first experimental demonstration of an SBC utilizing a solid-state battery, resulting in a reduced footprint. We achieve a power density of 0.34mW/mm3with 95% peak efficiency using a 0.33mm3battery while maintaining less than 3.1% output relative ripple without any output capacitor. Furthermore, the paper highlights the favorable scaling laws governing SBCs, suggesting a promising design space for IoT power management.

During their lifetime, wire harness can be modified due to external environment or unintentional technical action. It is therefore possible to see changes in the overall system behavior thus compromising system safety and reliability. There is, consequently diagnosis and maintenance issues. In modern cars, the electrical wire harness verification during manufacturing and afterwards maintenance and diagnosis become crucial due to increase of complexity and functional safety requirement. Estimating the line impedance (resistance and inductance) is beneficial to validate the wire harness during manufacturing and also to evaluate its health state over the vehicle lifetime. Integrate a very low wire inductance measurement system in one chip with reasonable area is a strong challenge. Because, a very small variation of below 0.1µH over a wide range of line inductance is desired. Then, measurement sensitivity requirement is very high. This paper describes a semi-conductor integrable method for measuring the wire inductance and detect a relative variation of wire length of about 10cm over 6m.

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This paper proposes a generalized averaging 1stharmonic state space model for Dual Active Bridge (DAB) converters fitting any triple phase-shift (TPS) modulation as well as classical modulation schemes. The model provides an analysis about steady state and AC behavior and about operating characteristics like RMS current and conducted emissions. Comparison of results with a full order SPICE simulation show a good agreement as well as with regard to the dynamic behavior prediction. With TPS modulation being the most effective means for optimizing the DAB's efficiency, the proposed approach avoids classical implementations' typical drawbacks such as the need for multiple models corresponding to the mapping of different operating space regions with respect to modulations or the need to pre-constrain control variables to specific switching modes. It can also help reduce the impact of large signal transients on the output filter or of the converter performance degradation with aging. The proposed model is suitable for designing a non-linear control scheme allowing better converter performances in relation to a classical one. The interest and accuracy of the proposed approach are shown through a 150W, 28V to 12V DAB design used for a flight computer power supply where the versatility in controller design and the converter efficiency optimization are required.

Electric vehicles use for urban mobility are rising with the new generation of 48 V powertrain technology. However, the challenge is to select onboard charger (OBC) topologies with less complex, economically feasible, and highly efficient battery chargers for these electric vehicles (EVs). At present, traditional multi-stage converters are being used by compromising efficiency, volume, weight, and cost. Single-stage OBC topologies can be designed by combining a few functions of a muli-stage coverter with a reduced number of components. They are aiming to eliminate issues related to multi-stage converters. However, the stress on power devices of single-stage OBCs can lead to other issues such as the requirement of expensive high power devices, thermal control, etc. This paper reviews single-phase, single-stage OBC topologies feasible for EVs with 48 V powertrain technology. Especially the isolated bidirectional AC–DC converters are considered as to include the vehicle-to-grid (V2G) capability.

This article describes a systematic and scalable electrostatic discharge (ESD) verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. The tool identifies the ESD protection network of a circuit thanks to a flexible topology-aware mechanism and converts the circuit description of this network into a directed graph whose edges are provided with quasistatic electrical behaviors inferred from the machine learning techniques detailed in a companion paper. A graph-based analysis establishes a risk rating cartography for all top-level pad-to-pad discharge combinations. The circuit reviewer, a chip designer, or an ESD expert can, therefore, assess the ESD performances of the ESD network under study and easily investigate potential ESD design weaknesses.

This article gives a detailed insight on a machine learning procedure to infer quasistatic quantities of electrostatic discharge (ESD) protection structures from their instance parameters in a netlist. It resorts to a dataset of transmission line pulse (TLP) I-V curves that have been obtained from numerous transient electrical simulations. The tuning of machine learning algorithms and the quantification of their generalized prediction performances on out-of-sample data are performed by means of nested cross-validation. Resulting fitted analytical models are encompassed in a tool called ESD IP Explorer in charge of providing a systematic and scalable ESD verification methodology. This tool, which has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures, is described in a former article.

Current viewing resistor (CVR) based measurement of a high frequency switching cell is presented. The drain current of the low-side GaN HEMT switch was measured at 100 kHz switching frequency for a maximum load current of 8 A and a dc input of 80 V. To analyze the results, both simulations and experiments were used. The parasitic elements of the PCB layout (i.e. calculated using the Ansys-Q3D Extractor software) were included in the simulation model. This paper explains the consequences of mounting CVRs in the common-source path of transistors compared to a circuit without a CVR. Simulation results are found to be in very good agreement with measurements. Hence, the simulation model can be used to estimate the current waveforms when it is not desirable to resort to intrusive measurement methods.

This paper describes the principle of an active gate driver to control the high current switching speed generated during the turn-on of GaN HEMT transistors. The proposed circuit requires a common-mode parasitic inductance of 1 nH to provide the necessary image of the current slope. The proposed scheme is comparable to a variation of gate resistance of one decade without the inconvenience of the gate resistance. The approach is first validated by circuit simulation then experimentally. The advantages of such an approach are then demonstrated thanks to the comparison with a conventional passive control method.

Although they can operate at high temperature, SiC devices require efficient thermal management. One solution is to use a dual-side cooling packaging, where heat can be extracted through two surfaces. Here, such a package is presented, using only materials which can operate at high temperature (> 200°C): ceramic substrates, silver sintering, fluorinated parylene. Due to the small feature size of the SiC dies used, a special care is given on the etching resolution of the substrates. The complete manufacturing process is presented, and some characterization results are given to demonstrate that the package is operational.

The electrical conversion in aerospace applications faces important issues to gain in reliability, efficiency and profitability. This paper focuses on preliminary analyses towards condition monitoring for new power modules based on 2D interconnection of SiC power MOSFETs for 600V, 90A applications. Power modules are so far lab-scale samples for which failure analyses and ageing have not been addressed. Based on a literature review, a test plan has been established to trigger expected failure modes. Using temperature-sensitive-electrical parameters, it is expected to identify signatures of failures. In a short-term, laws of failures will be evaluated based on signatures for the prognostic of the lifetime consumption of the module. This paper details the experimental setup, calibration steps and data monitoring towards identification of ageing signatures. Data analyses are also detailed.

This paper presents a black box small-signal modeling of a low-dropout (LDO) voltage regulator. The small-signal model is derived for each part of the system around an operating point. Then, the closed-loop transfer-functions are obtained to build a five port network model of the LDO. The analytical solution is validated by simulation comparison with transistor-level implementation of a PMOS LDO in a 90nm CMOS process from STMicroelectronics. Due to the hand calculation difficulty, we proposed an automated extraction flow based on the QZ algorithm. The flow is verified with the model extraction of a complex PMOS LDO, designed in a 55nm STMicroelectronics CMOS process.

A digital current and voltage predictive controller (CVP) is proposed for high switching frequency, low power SMPS. The predictions of the inductor current and capacitor output voltage are performed simultaneously by adopting a flexible PWM pattern that enables dynamic adjustment of the time of the voltage events. The CVP controller preserves the merits of predictive current-mode control and allows to further improve the dynamic performances. With the knowledge of the inductor current, the performances of the CVP controller are analyzed compared to a deadbeat controller. Experimental results of a current sensorless implementation verify better closed-loop performances than those of PID, RST and sliding-mode controllers. The lab-scale prototype implemented in an FPGA supports a switching frequency up to 4 MHz only limited by the discrete buck converter.

This paper presents the application of predictive deadbeat control to the high switching frequency DC/DC Single-Ended Primary Inductor Converter (SEPIC). An extended Kalman observer with load variation estimation is designed to achieve current sensorless operation of the controller. A hybrid Delta-Sigma (Δ-Σ) Digital Pulse Width Modulation (DPWM) is used to effectively achieve 11-bit resolution at high-frequency and reduce the system clock frequency. The proposed DPWM along with the predictive deadbeat control algorithm is validated by using a Virtex-II FPGA. Experimental studies are conducted for a laboratory prototype with switching frequency of 500kHz. Simulation and experimental results prove the performance of the proposed solution.

This paper presents a novel digital controller for the high-switching-frequency buck converter based on the principle of predictive control. Compared with a traditional current-mode predictive controller, the prediction of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal that can dynamically adjust the time of voltage jump. It accelerates the convergence rate during transient states, while inherently preserving the rejection of power and reference perturbations. The analysis of controller's operation illustrates the dual-state-variable predictive attributes that lead to the digital implementation. To further enhance the power efficiency of the controller, an 1-1 MASH Σ- Δ DPWM with a feasible dither generation module is proposed to restrain the idle-tone effects without deteriorating the closed-loop stability as well as to preserve reasonable cost in silicon area. Experimental results verify closed-loop operations at switching frequency up to 4 MHz only limited by the discrete buck converter. The converter is well regulated over a large output range with excellent dynamic performances.

SRAM 6T bitcell suffers many limitations in advanced technology nodes among which varaibility issues. Various alternatives have been experimented and the paper focuses the 5T portless bitcell. Read and write operations are operated by varying voltage conditions. The results in have been reviewed in CMOS 32nm and improvements have been provided. The bitcells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bitcell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption. The paper details the portless operation and current-mode reading based an simulation results. A matrix testchip is currently under fabrication in bulk CMOS 32nm.

We present Worldsens,a prototyping and development work for wireless sensor protocols and applications.Our relies on two simulators,WSim and WSNet, and proposes a full simulation and performance estimation embedded platforms with instruction and radio byte curacy.During this demo,we propose to demonstrate the interest of the two simulators in stand-alone and in cooperative use.

In order to reduce production costs of RF devices, it is important to remove bad circuits very early in the production flow. It is all the more true for dies designed to be integrated in complex systems. Thus highly efficient RF wafer testing is mandatory for those applications to prevent the loss of assembled systems due to defective RF dies. The problem is that current RF probing technologies hardly fulfil the industrial test requirements in terms of accuracy, reliability and cost. The proposed method proves to be a very interesting alternative to validate RF parameters with no need of expensive RF equipments (RF probes and RF automated test equipments (ATE)). A new test strategy based on DC or very low frequency (LF) measurements, which allows the elimination of expensive RF tests, is presented. The main idea is to insert some simple design for test (DfT) circuitry within the chip. This DfT provides relevant information on the structural behavior of the device blocks. The internal node data are additional to standard DC test measurements like power supply current or advanced DC test signatures (e.g. Vdd ramping), and LF measurements like gain in loopback mode. Since RF performance of each block is directly related to such structural data, it is possible to predict the RF characteristics of the blocks without time consuming RF measurements. RF parameters estimation is performed using nonlinear artificial neural networks