A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire routing congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based routing congestion constraints.

Clock gating is recognized as one of the most effective techniques to reduce the dynamic power consumption. Many research efforts have been paid to build activity-driven clock trees for low power designs. On the other hand, as the feature size continues to shrink, the on-chip-variation (OCV) effect has become a serious concern, especially for the clock skew of the top-level clock tree. Based on this observation, in this paper, we present the first work for the synthesis of OCV-aware top-level activity-driven clock trees. In our approach, the clock skew variation is considered during the top-level activity-driven clock tree synthesis. Our objective is to minimize the weighted sum of the worst timing slack and the power consumption. Compared with previous works, benchmark data consistently show that our approach can greatly increase the worst timing slack with a small overhead on the power consumption.

We propose a microcode-optimizing method targeting a programmable DSP processor. Efficient generation of microcodes is essential to better utilize the computation power of a DSP processor. Since most state-of-the-art DSP processors feature some sort of irregular architectures and most DSP applications have nested loop constructs, their code generation is a nontrivial task. In this paper, we consider two features frequently found in contemporary DSP processors — structural pipelining and heterogeneous registers. We propose a code generator that performs instruction scheduling and register allocation simultaneously. The proposed approach has been implemented and evaluated using a set of benchmark core algorithms. Simulation of the generated codes targeted towards the TI TMS320C40 DSP processor shows that our system is indeed more effective compared with a commercial optimizing DSP compiler.

High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain.Both application-speci c integrated circuits (A-SICs) and application-speci c instruction-set processor (ASIPs) have been frequently designed using the HLS approach.Since most ASIP and DSP processors provide multiple addressing modes, and, in addition to classical constraint on the number of function units, registers, and buses, there a r e many resource usage rules, special considerations need t o b e p aid to the optimizing code generation problem.In this paper we propose three t r ansformation techniques, data management, data ordering, and transformational retiming, for storage optimization during code generation.With these transformations, some scheduling bottlenecks are eliminated, redundant instructions removed, and multiple operations mapped onto a single one.The proposed t r ansformations have been implemented in a software system called Theda:MS.A set of benchmark programs has been used to evaluate the eectiveness of Theda:MS.M e asurement on the synthesized c o des targeted towards the TI-TMS320C40 DSP processor shows that the proposed approach is indeed very eective.