The Martian rover Zhurong represents the first deep-space exploration rover to be equipped with full polarimetric ground-penetrating radar (GPR). This radar collects multi-polarization data that capture the rotation of the electric vector, thereby providing insights into the type, surface roughness, and dielectric properties of subsurface objects. However, most studies have relied on conventional analysis methods, thereby failing to exploit the full potential of all four data channels. In this study, we utilize simulated 3D polarimetric data derived from subsurface models representative of the mission’s landing area, which comprises the Martian atmosphere, surface soil, subsurface ice, rocks, and bedrock layers. The simulation results facilitate an analysis of the scattering characteristics of subsurface targets, such as stones and fractures. We propose a false-colour imaging and processing method that enhances radar image quality and improves the precision of permittivity estimation to 90%. Furthermore, the scattering spectrum derived from Freeman decomposition is employed to classify various subsurface structures while providing information on their types, sizes, and dielectric properties. Ultimately, the proposed method is applied to analyze the radar data acquired by the Zhurong rover on Mars.

Lunar craters are critical for studying the Moon’s geological evolution and impact history, making their efficient identification vital for planetary science. To address the limitations of traditional methods in detecting craters across complex terrains and multiple scales, this paper proposes a novel Dual Cross-Modal Weighted Attention Feature Fusion Network (DCMWAF-Net) for multi-scale lunar crater detection. The model integrates Kaguya TC Morning imagery and SLDEM2015 digital elevation model (DEM) data, leveraging a Multi-modal Feature Extractor (MFE) to capture morphological and topographic features. A Cross-Modal Weighted Attention Feature Fusion (CMWAF) module, combined with the Convolutional Block Attention Module (CBAM), enables adaptive fusion of imagery and topographic features. Additionally, a Multi-Scale Feature Aggregation (MSFA) module, employing a bidirectional pyramid structure, enhances feature integration, while the Detection Head (DH) module, with an optimized anchor-box mechanism, improves localization accuracy, significantly boosting the detection of multi-scale craters. Experimental results demonstrate that DCMWAF-Net achieves superior performance in the test region spanning 55°–59°W longitude and 45°–48°N latitude, with an overall recall of 93.26% and precision of 90.71%. Compared to single-modal methods using only imagery or DEM and traditional data fusion models, DCMWAF-Net improves recall by 3%–14% and achieves a matching rate of 93.24% against ground-truth annotations. Furthermore, the model successfully identified and confirmed 2,138 new craters, and predicted a total of 174,806 craters in the Chang’e-5 landing region, significantly expanding the existing crater database while enhancing the accuracy and efficiency of crater detection in complex terrain environments.

The navigation camera images of Zhurong Rover can be utilized to reconstruct high-resolution 3D models, which play a vital role in scientific analysis and engineering tasks. Existing studies can effectively obtain individual block 3D models within localized regions. However, due to the unique operational and environmental conditions of the Mars rovers, it is difficult to provide corresponding points as well as a unified coordinate system for all individual block models. This also results in reconstructed models that cannot be validated and corrected, and it is not possible to stitch multiple individual models together. Fortunately, the Inertial Measurement Unit (IMU) of the Zhurong Rover provides continuous coordinate information along the trajectory. Building upon this, we proposed a rover-oriented model reconstruction (ROMR) method that effectively corrects the drift error of IMU track. Then, it converts all individual block models, derived from navigation camera images, into a unified coordinate system, ultimately achieving a spatially continuous 3D model. We validated the ROMR method using the first batch of data from the Zhurong Rover (the first 46 navigation points) and generated a high-resolution 3D model as well as a precise Digital Elevation Model (DEM) along the trajectory. Within a 10 m radius of the travel path, the average resolution can reach 5 cm/pixel. Subsequently, we analyzed the fine landform texture and weathering effects on the Martian surface, yielding crucial insights to unravel the paleoclimate changes on Mars.

Ground-penetrating radar (GPR) is one of the powerful tools to reveal the subsurface structure of planetary bodies and has obtained great success in planetary exploration. Permittivity estimation with radar data can provide the geometric and physical parameters of near-surface materials of planetary bodies. In this study, we propose to use the adaptive genetic algorithm (AGA), which can prevent the result from converging to local minima and not subject to the initial model setting, to improve the reliability and efficiency of the estimation of the permittivity with the GPR data. Based on the convolution forward model and simulation data, the inversion method with AGA has demonstrated an excellent performance on curve fitting. The statistical probability of the estimation result proves that the AGA, compared with the standard genetic algorithm (SGA), has the ability of sustainable evolution and well convergence in the high dimension problem. In the simulation experiments, the mean value of the 95% confidence interval of the permittivity inversion results narrowed from 8.4 to 2.6. Next, we used AGA to GPR experimental data collected in the lava tube field on the Earth and successfully detected the low permittivity characteristics within the lava tubes. This result can provide a workable inversion method for finding lava tubes and other unknown subsurface features in future planetary exploration, especially lack of background information in planetary or polar exploration.

On 15th May 2021, the Tianwen-1 (TW-1) successfully landed on the surface of Mars within the southern Utopia Planitia. It delivered a rover named Zhurong equipped with ground penetrating radar (GPR), a device that can investigate the thickness and structure of the geological layers below the martian surface. The hyperbola method is commonly used for extracting dielectric property variations with depth from GPR data to aid the interpretation of the subsurface structure and material composition. This study analyzes the advantages and drawbacks of three hyperbola methods with different geometric models. Next, it proposes a new method aiming to use the highly precise, yet complex geometric model and address issues caused by its solving process. We also analyze the influencing factors contributing to measurement errors and design corresponding criteria for measurement point selection to mitigate errors. The average error of the proposed method is less than 5% for a depth of up to 9 m. We employed the proposed method to obtain the dielectric constant distribution in the shallow surface layer of the TW-1 landing zone to a depth of up to 16 m. The dielectric constant is mainly concentrated between 2 and 8 m and increases gradually with depth. Below 2 m, the dielectric constant is about 5.1 and the density is about 2.5 g/cm3. The stratification and density variation can be inferred from the dielectric constant distribution diagram.

The two microwave radiometers (MRMs) onboard the Chinese Lunar explorers Chang’E-1 (CE-1) and Chang’E-2 (CE-2) are considered to be identical instruments, yet the results differ, with lunar brightness temperatures obtained by CE-2 generally lower than those of CE-1 in all four frequency channels. The differences can reach over 10 K in the same local time. We propose a recalibration model that takes into account the brightness temperature constant shift of the MRM equipment and the possibility that the Chang’E calibration antennas may have inadvertently picked up some thermal radiation from the lunar surface due to its field of view cutting into the lunar surface. These effects may have negatively influenced the accuracy of the simple two-point calibration procedure and led to the difference between the available MRM level 2C data from CE-1 and CE-2. Our recalibration model determines the correction parameters through a statistical analysis that minimizes the mismatch between the two datasets. Recalibration of the level 2C data based on our recalibration model successfully realigns the microwave brightness temperatures measured by CE-1 and CE-2.

Three upcoming Martian missions will deploy a ground-penetrating radar (GPR) to reveal the fine-resolution subsurface structure and dielectric properties of materials beneath the surface. Numerical forward simulations of radar echo using a model of the near-surface structure at the landing site can provide a valuable reference for processing and interpretation of future radar data collected on Mars. In this study, based on the geological information of the Jezero crater, a detailed stratigraphic model of the near-surface structure is derived, which includes several key features, for example, the randomness of the medium, terrain, and cracks. To identify correctly the reflections of subsurface interfaces and fractures from the radar image, a$v(z$) f-k migration is carried out, the performance of which is evaluated using the GPR data obtained near Antarctic Zhongshan Station since the electrical properties of Antarctic glaciers and Martian materials are to some extent comparable. The results in this work show that compared with common migration algorithm, the$v(z$) f-k method not only improves the clarity of radar image but also provides the permittivity profiles to infer the composition of the substrate, leading to a better understanding of Martian near-surface geology.

Nanophotonic networks, a potential candidate for future networks on-chip, have been challenged for their reliability due to several device-level limitations. One of the main issues is that fabrication errors (a.k.a. process variations) can cause devices to malfunction, rendering communication unreliable. For example, the microring resonator, a preferred optical modulator device, may not resonate at the designated wavelength under process variations (PVs), leading to communication errors and bandwidth loss. This article proposes a series of solutions to the wavelength drifting problem of microrings and subsequent bandwidth loss problem of an optical network, due to PVs. The objective is to maximize network bandwidth through proper arrangement among microrings and wavelengths with minimum power requirements. Our arrangement, called “MinTrim,” solves this problem using simple integer linear programming, adding supplementary microrings, and allowing flexible assignment of wavelengths to network nodes as long as the resulting network presents maximal bandwidth. Each step is shown to improve bandwidth provisioning with lower power requirements. Evaluations on a sample network show that a baseline network could lose more than 40% bandwidth due to PVs. Such loss can be recovered by MinTrim to produce a network with 98.4% working bandwidth. In addition, the power required for arranging microrings is 39% lower than the baseline. Therefore, MinTrim provides an efficient PV-tolerant solution to improving the reliability of on-chip photonics.

As technology scales, thermal management for multicore architectures becomes a critical challenge due to increasing power density. Existing power budgeting techniques focus on maximizing performance under a given power budget by optimizing the core configurations. In multicore era, a chip-wide power budget, however, is not sufficient to ensure thermal constraints because the thermal sustainable power capacity varies with different threading strategies and core configurations. In this article, we propose two models to dynamically estimate the thermal sustainable power capacity in homogeneous multicore systems: uniform power model and nonuniform power model . These two models convert the thermal effect of threading strategies and core configurations into power capacity, which provide a context-based core power capacity for power budgeting. Based on these models, we introduce a power budgeting framework aiming to improve the performance within thermal constraints, named as TSocket. Compared to the chip-wide power budgeting solution, TSocket shows 19% average performance improvement for the PARSEC benchmarks in single program scenario and up to 11% performance improvement in multiprogram scenario. The performance improvement is achieved by reducing thermal violations and exploring thermal headrooms.

One of the design challenges for the emerging 3D ICs is the power integrity. With multiple dies stacked vertically, the voltage droop may result in severe power integrity issues. In this paper, we first analyze the impact of application behaviors on voltage droop in a 3D power supply network (PDN) and observe that voltage droop is extremely imbalanced either across different layers or among the cores in the same layer. Based on the observation, we propose Swimming Lane, a hardware/software co-design method with two key schemes: (1) Mitigating the interference among different dies via a layer-independent scheme, and (2) balancing the intra-layer voltage droop and reducing the worst-case margin via OS scheduling. Compared to conventional designs, our method can reduce power consumption by 18%, worst-case voltage droops by 13%, and the number of voltage violations by 40%.

As technology scales, thermal management for multi-core architectures becomes a critical challenge due to increased power density and higher integration density. Existing power budgeting techniques focus on maximizing performance under a given power budget by optimizing the core dynamics. However, in multi-core era, a chip-wide power budget is not sufficient to ensure thermal constraints because the thermal sustainable power capacity varies with different threading strategies and core configurations. In this paper, we propose a model which estimates the thermal sustainable power capacity considering these two run-time factors. The model converts the thermal effect of threading strategies and core configurations into power capacity, which provides a context-based power budget for the power budgeting. Based on this model, we introduce a power budgeting framework aiming to optimize the performance within thermal constraints, named as TSocket. Compared to the chip-wide power budgeting solution, TSocket shows 19% of performance improvement for the PARSEC benchmarks by reducing thermal violations and providing extra power budget for performance improvement.

The emerging on-chip optical interconnection has become a promising candidate for future network design because of its advantages in high bandwidth density, low propagation delay and dynamic power consumption. However, a key challenge of on-chip optics is the high static power consumption which dominates the total network power. Hence, it is imperative to design an energy-efficient optical network architecture with high throughput while consuming low static power. In conventional optical crossbars, static channel allocation results in low channel utilization and network throughput, while full channel sharing requires a significant number of microrings, which incurs high static power.

Nanophontonic networks, a potential candidate for future networks on-chip, have been challenged for their reliability due to several device-level limitations. One of the main issues is that fabrication errors (a.k.a. process variations) can cause devices to malfunction, rendering communication unreliable. For example, microring resonator, a preferred optical modulator device, may not resonate at the designated wavelength under process variations (PV), leading to communication errors and bandwidth loss. This paper proposes a series of solutions to the wavelength drifting problem of microrings and subsequent bandwidth loss problem of an optical network, due to PV. The objective is to maximize network bandwidth through proper arrangement among microrings and wavelengths with minimum power requirement. Our arrangement, called “MinTrim”, solves this problem using simple integer linear programming, adding supplementary microrings and allowing flexible assignment of wavelengths to network nodes as long as the resulting network presents maximal bandwidth. Each step is shown to improve bandwidth provisioning with lower power requirement. Evaluations on a sample network show that a baseline network could lose more than 40% bandwidth due to PV. Such loss can be recovered by MinTrim to produce a network with 98.4% working bandwidth. In addition, the power required in arranging microrings is 39% lower than the baseline. Therefore, MinTrim provides an efficient PV-tolerant solution to improving the reliability of on-chip phontonics.

The number of on-chip cores of modern chip multiprocessors (CMPs) is growing fast with technology scaling. However, it remains a big challenge to efficiently support cache coherence for large scale CMPs. The conventional snoopy and directory coherence protocols cannot be smoothly scaled to many-core or thousand-core processors. Snoopy protocols introduce large power overhead due to enormous amount of cache tag probing triggered by broadcast. Directory protocols introduce performance penalty due to indirection, and large storage overhead due to storing directories. This paper addresses the efficiency problem when supporting cache coherency for large-scale CMPs. By leveraging emerging optical on-chip interconnect (OP-I) technology to provide high bandwidth density, low propagation delay and natural support for multicast/broadcast in a hierarchical network organization, we propose a composite cache coherence (C 3) protocol that benefits from direct cache-to-cache accesses as in snoopy protocol and small amount of cache probing as in directory protocol. Targeting at quickly completing coherence transactions, C 3 organizes accesses in a three-tier hierarchy by combining a mix of designs including local broadcast prediction, filtering, and a coarse-grained directory. Compared to directory-based protocol [18], our evaluations on a thousand-core CMP show that C 3 improves performance by 21%, reduces network latency of coherence messages by 41 % and saves network energy consumption by 5.5 % on average for PARSEC applications.

Technology scaling has led to the integration of many cores into a single chip. As a result, on-chip interconnection networks start to play a more and more important role in determining the performance and power of the entire chip. Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multi-core processors. However the virtual-channel (VC) buffers in the NoC consume significant dynamic and leakage power of the system. To improve the energy efficiency of the router design, it is advantageous to use small buffer sizes while still maintaining throughput of the network. This paper proposes two new virtual channel allocation (VA) mechanisms, termed Fixed VC Assignment with Dynamic VC Allocation (FVADA) and Adjustable VC Assignment with Dynamic VC Allocation (AVADA). The idea is that VCs are assigned based on the designated output port of a packet to reduce the Head-of-Line (HoL) blocking. Also, the number of VCs allocated for each output port can be adjusted dynamically. Unlike previous buffer-pool based designs, we only use a small number of VCs to keep the arbitration latency low. Simulation results show that FVADA and AVADA can improve the network throughput by 41% on average, compared to a baseline design with the same buffer size. AVADA can still outperform the baseline even when our buffer size is halved. Moreover, we are able to achieve comparable or better throughput than a previous dynamic VC allocator while reducing its critical path delay by 60%. Our results prove that the proposed VA mechanisms are suitable for low-power, high-throughput, and high-frequency on-chip network designs.

A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and reduce the delay of interconnects significantly across the dies. However, a major challenge in 3D technology is the increased power density, which gives rise to the concern of heat dissipation within the processor. High temperatures trigger voltage and frequency throttlings in hardware, which degrade the chip performance. Moreover, high temperatures impair the processor's reliability and reduce its lifetime. To alleviate this problem, we propose in this paper an OS-level scheduling algorithm that performs thermal-aware task scheduling on a 3D chip. Our algorithm leverages the inherent thermal variations within and across different tasks, and schedules them to keep the chip temperature low. We observed that vertically adjacent dies have strong thermal correlations and the scheduler should consider them jointly. Compared with other intuitive algorithms such as a Random and a Round-Robin algorithm, our proposed algorithm brings lower peak temperature and average temperature on-chip. Moreover, it can remove, on average, 46 percent of thermal emergency time and result in 5.11 percent (4.78 percent) performance improvement over the base case on thermally homogeneous (heterogeneous) floorplans.

The proliferation of chip multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller banks that are interconnected through packet-based network-on-chip (NoC). With increasing number of cores and cache banks integrated on a single die, the on-chip network introduces significant communication latency and power consumption. In this paper, we propose a novel scheme that exploitsfrequentvaluecompression to optimize the power and performance of NoC. Our experimental results show that the proposed scheme reduces the router power by up to 16.7%, with CPI reduction as much as 23.5% in our setting. Comparing to the recent zero pattern compression scheme, thefrequentvaluescheme saves up to 11.0% more router power and has up to 14.5% more CPI reduction. Hardware design of the FV table and its overhead are also presented.

Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and high-bandwidth fabric for interconnect design. The advent of the 3D technology has provided further opportunity to reduce on-chip communication delay. However, the design of the 3D NoC topologies has important distinctions from 2D NoCs or off-chip interconnection networks. First, current 3D stacking technology allows only vertical inter-layer links. Hence, there cannot be direct connections between arbitrary nodes in different layers — the vertical connection topology are essentially fixed. Second, the 3D NoC is highly constrained by the complexity and power of routers and links. Hence, low-radix routers are preferred over high-radix routers for lower power and better heat dissipation. This implies long network latency due to high hop counts in network paths. In this paper, we design a low-diameter 3D network using low-radix routers. Our topology leverages long wires to connect remote intra-layer nodes. We take advantage of the start-of-the-art one-hop vertical communication design and utilize lateral long wires to shorten network paths. Effectively, we implement a small-to-medium sized clique network in different layers of a 3D chip. The resulting topology generates a diameter of 3-hop only network, using routers of the same radix as 3D mesh routers. The proposed network shows up to 29% of network latency reduction, up to 10% throughput improvement, and up to 24% energy reduction, when compared to a 3D mesh network.

A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and reduce the delay of interconnects across the dies. However, a major challenge in 3D technology is the increased power density which brings the concern of heat dissipation within the processor. High temperatures trigger voltage and frequency throttlings in hardware which degrade the chip performance. Moreover, high temperatures impair the processorpsilas reliability and reduce its lifetime. To alleviate this problem, we propose in this paper an OS-level scheduling algorithm that performs thermal-aware task scheduling on a 3D chip. Our algorithm leverages the inherent thermal variations within and across different tasks, and schedules them to keep the chip temperature low. We observed that vertically adjacent dies have strong thermal correlations, and the scheduler should consider them jointly. Our proposed algorithm can remove on average 54% of hardware DTMs and result in 7.2% performance improvement over the base case.