Demo Data from EDBT 2026 / reviewers in the wild / expert
M. D. Derk
dblp:14/581
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Distributed systems · 30% Hardware reliability and fault tolerance · 30% Reconfigurable computing and FPGAs · 30% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Distributed systems
fault tolerance |
0.0 | 1 | 1998 | Reconfiguration for Fault Tolerance Using Graph Grammars · ACM Trans. Comput. Syst. 1998 |
Reconfigurable computing and FPGAs › dynamic reconfiguration
processor array reconfiguration |
0.0 | 1 | 1998 | Reconfiguration for Fault Tolerance Using Graph Grammars · ACM Trans. Comput. Syst. 1998 |
Hardware reliability and fault tolerance
reconfiguration |
0.0 | 1 | 1998 | Reconfiguration for Fault Tolerance Using Graph Grammars · ACM Trans. Comput. Syst. 1998 |
Parallel and multicore computing
array processor |
0.0 | 1 | 1998 | Reconfiguration for Fault Tolerance Using Graph Grammars · ACM Trans. Comput. Syst. 1998 |
Methods — techniques the papers use, named apart from their topics
graph grammar · 0.0distributed algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | Reconfiguration for Fault Tolerance Using Graph GrammarsabstractReconfiguration for fault tolerance is a widely studied field, but this work applies graph grammars to this discipline for the first time. Reconfiguration Graph Grammars (RGG) are defined and applied to the definition of processor array reconfiguration algorithms. The nodes of a graph are associated with the processors of a processor array, and the edges are associated with those interprocessor communication lines that are active. The resulting algorithms for dynamic (run-time) reconfiguration are efficient and can be implemented distributively. M. D. Derk, Linda DeBrunner |
ACM Trans. Comput. Syst. | 1 |