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Jeffrey T. Oplinger

dblp:14/6089 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 33% Parallel and multicore computing · 33% Hardware reliability and fault tolerance · 33%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › system reliability
software reliability
0.012002
Enhancing software reliability with speculative threads · ASPLOS 2002
Processor architecture and microarchitecture
speculative execution
0.012002
Enhancing software reliability with speculative threads · ASPLOS 2002
Parallel and multicore computing › speculative parallelization
thread-level speculation
0.012002
Enhancing software reliability with speculative threads · ASPLOS 2002
Concurrent programming
transactional memory
0.012002
Enhancing software reliability with speculative threads · ASPLOS 2002
YearPublicationVenuePosition
2002 Enhancing software reliability with speculative threads
abstract
This paper advocates the use of a monitor-and-recover programming paradigm to enhance the reliability of software, and proposes an architectural design that allows software and hardware to cooperate in making this paradigm more efficient and easier to program.We propose that programmers write monitoring functions assuming simple sequential execution semantics. Our architecture speeds up the computation by executing the monitoring functions speculatively in parallel with the main computation. For recovery, programmers can define fine-grain transactions whose side effects, including all register modifications and memory writes, can either be committed or aborted under program control. Transactions are implemented efficiently by treating them as speculative threads.Our experimental results suggest that monitored execution is more amenable to parallelization than regular program execution. Code monitoring is sped up by a factor of 1.5 by exploiting single-thread instruction-level parallelism, and by an additional factor of 1.6 using thread-level speculation. This results in an overall improvement of 2.5 times and a sustained 5.4 instructions-per-cycle performance. A monitored execution that used to be 2.5 times slower executes with a degradation of only 12% when compared to the performance on the baseline machine. We also show that the concept of fine-grain transactional programming is useful in catching buffer overrun errors through a number of real-life examples.
Jeffrey T. Oplinger, Monica S. Lam
ASPLOS1