Chi-Chang Liaw

dblp:14/6902 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
high-level synthesis
0.011984
A high level synthesis tool for MOS chip design · DAC 1984
Electronic design automation › hardware verification and test
fault testing
0.011981
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits · IEEE Trans. Computers 1981
Electronic design automation
hardware verification and test
0.011981
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits · IEEE Trans. Computers 1981
Electronic design automation › hardware verification and test › fault testing
intermittent fault testing
0.011981
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits · IEEE Trans. Computers 1981
Electronic design automation › hardware verification and test
sequential circuit testing
0.011981
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits · IEEE Trans. Computers 1981
Electronic design automation › hardware verification and test
test generation
0.011981
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits · IEEE Trans. Computers 1981
Electronic design automation › hardware verification and test › fault diagnosis
intermittent faults
0.011981
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits · IEEE Trans. Computers 1981

Methods — techniques the papers use, named apart from their topics

test-experiment design · 0.0
YearPublicationVenuePosition
1984 A high level synthesis tool for MOS chip design
Jean-Pierre Dussault, Chi-Chang Liaw, Michael M. Tong
DAC2
1981 State Diagram Approach for Functional Testing of Control Section
Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya
ITC1
1981 Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits
abstract
Practical solutions have not been obtained from the previous papers addressing the problem of testing intermittent faults in sequential circuits. Existing methods are only suitable for small sequential circuits. This correspondence presents a new technique to design test-experiments for intermittent faults which can conveniently be used for relatively more complex synchronous sequential circuits.
Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya
IEEE Trans. Computers1