To meet challenges of deep-subwavelength technologies (particularly 130 nm and following), lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and RETs like altPSM. For emerging technologies (65 nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the design-silicon flow. This has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. We have been exploring how design might take advantage of these restrictions, and present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of OPC/RET algorithms and the accuracy of models of manufactured products. We also believe that the underlying technology, including simulation and analysis, may be applicable to a variety of approaches to design for manufacturability (DFM).

Every year, the design and EDA communities are besieged by dire warnings about the impending doom of "design as we know it." Every year, another unpleasant physical effect from the evil depths of deep submicron physics surfaces, compromising our designs in new and vile ways. Every year, the same story: more nanometer woes. Rather than endorse a new winner in this year's race for the next worst thing from the nanometer arena, this panel gathers a set of world-class technology experts to debate what effects are hiding just around the next corner, waiting to pounce on the unwary tool or chip designer. Which among these is really the most important, when will it happen, and why.

Every 18 to 24 months, the areal density of VLSI doubles and the predicted date for the End Of CMOS Scaling is pushed out approximately 18 to 24 months. This rate of growth has been controlled mainly by the increasing capabilities of lithographic patterning. However, the rate of improvement of lithography systems in key parameters such as illumination wavelength has begun to slow. To make up the shortfall, lithography has increasingly turned to using CAD tools to transform the geometric shapes in designs into shapes on photomasks which have been compensated for systematic pattern-distorting effects. As the requirements for this compensation grow, however, it becomes increasingly difficult to hide in post-tapeout data preparation, and must be considered in back-end design tools and methodologies. We describe a number of the challenges to lithographic patterning, highlighting the factors that limit physical scaling and introduce the layout-to-mask shape transformations that compensate for these limitations. We describe the implementation of these transformations in general-purpose and specialized CAD tools, pointing out challenges like growth of computation effort. Finally, we describe how limitations of post-tapeout compensation drive the need for litho-aware design tools, showing examples in cell design, place-and-route, and layout migration.

Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

The object-oriented language for image and vision environments (OLIVE), which is intended to make it easier to develop efficient, portable applications is presented. OLIVEs principal object types, called images and loci (abstractions of point sets and geometric entities), and their corresponding operations, including the use of locuses as generalized indexes for images, are defined. Several examples of OLIVE for typical image processing and machine vision tasks are presented. Issues concerning the implementation of OLIVE, including a hardware architecture that simplifies the implementation while enhancing its performance, are discussed.>

A parallel algorithm is presented for labeling the connected components of multicolored digital images. The algorithm takes advantage of the bottom-up divide-and-conquer strategy applied in tree and pyramid architectures but only requires a mesh topology. To support nonlocal communication, where meshes perform poorly, the authors propose the polymorphic torus, a regular mesh interconnection network in which each node is able to dynamically interconnect its ports, depending on its own data. By having each node properly drive such an interconnection, communication links between processors get established and disconnected and, as a result, the effective network diameter is reduced. The proposed connected-component labeling algorithm requires O( square root n) steps for a square root n* square root n multicolored image of an n-processor polymorphic torus, which is the same performance achieved in a tree architecture with 2n-1 processors. The lower number of processors and the simpler topology of polymorphic torus (vs. tree) make it a very suitable approach to mesh augmentation for intermediate-level vision applications.>

Special-purpose sensors and hybrid mechanical systems have been developed to assemble advanced electronic circuits. State-of-the-art robot systems that are used for electronic assembly and accuracy requirements for the developing surface mount technology are reviewed, showing the need for improved robot positioning capability. Examples of laboratory experiments that demonstrated successful precision assembly or testing using an ordinary robot, a micropositioner, and an optical sensing system are given. These involve fiber-optic sensing, machine-vision endpoint sensing, and hybrid tactic-vision endpoint sensing.>