Design teams designing modern multi-million gate systems-on-chip (SoCs) are being adversely affected by the lack of desired chip assembly solutions in addition to the challenges due to variability in nanometer technologies. Abstractions, bad pin assignments, incorrect block budgets, incorrect clock insertion delay budgets, lack of variability aware analysis engines, and lack of concurrent optimization capabilities often lead to chip failures, reduced yield, missed schedule and lost performance.Due to the late surprises in chip assembly, design teams have rushed to incorporate chip assembly as part of concurrent engineering with the block implementation. A new paradigm and tool set that enables efficient multi-million gate chip assembly while concurrently analyzing and optimizing across all variability scenarios is critical for nanometer hierarchical flows.In this paper we will review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.

With geometries shrinking in nanometer technologies, crosstalk noise becomes a critical issue. Modern designs like system-on-chips have millions of noise-prone nodes, mandating fast yet accurate crosstalk noise analysis techniques. Using linear circuit model, static noise analysis can efficiently estimate crosstalk noise. Traditionally in static noise analysis, drivers' holding resistances are precharacterized without considering the potential impact of crosstalk noise. However, crosstalk induced voltage fluctuation strongly affects the behavior of nonlinear drivers. When facing different coupling interconnects and hence crosstalk noise, a driver's holding resistance can change dramatically. In nanometer circuits, this substantial variation of nonlinear drivers cannot be totally ignored. To achieve high-quality in noise estimation yet maintain the efficiency of linear circuit model, we propose a novel interconnect coupling-aware driver modeling method. Based on layout-extracted interconnect parameters and precharacterized driver models, an effective holding resistance is calculated to capture the impact of the nonlinear driver. Multiple aggressors with synchronous and asynchronous switching activities are also considered. The proposed method is simple, efficient, and enables on-the-fly calculation of the effective holding resistance. Experiments show that with negligible computation overhead, the coupling-aware driver modeling methodology can significantly improve the quality of static noise analysis.