The increasing gap between the growth of datacenter traffic and electrical switch capacity is expected to worsen due to the slowdown of Moore's law, motivating the need for a new switching technology for the post-Moore's law era that can meet the increasingly stringent requirements of hardware-driven cloud workloads. We propose Sirius, an optically-switched network for datacenters providing the abstraction of a single, high-radix switch that can connect thousands of nodes---racks or servers---in a datacenter while achieving nanosecond-granularity reconfiguration. At its core, Sirius uses a combination of tunable lasers and simple, passive gratings that route light based on its wavelength. Sirius' switching technology and topology is tightly codesigned with its routing and scheduling and with novel congestion-control and time-synchronization mechanisms to achieve a scalable yet flat network that can offer high bandwidth and very low end-to-end latency. Through a small-scale prototype using a custom tunable laser chip that can tune in less than 912 ps, we demonstrate 3.84 ns end-to-end reconfiguration atop 50 Gbps channels. Through large-scale simulations, we show that Sirius can approximate the performance of an ideal, electrically-switched non-blocking network with up to 74-77% lower power.

The paper discusses results of integration of experimental campaign with CFD studies, where a small wind turbine placed inside a wind tunnel test section has been examined. Investigation included determination of model size influence on flow blockage effects. The CFD model helps to reduce time spent at the experimental stand and, therefore, costs pointing to the model with acceptable dimensions. CFD has been also used to anticipate the loads that may be exerted on the model thus helping to understand necessary measures in the upcoming aeromechanics study of the construction. The study concerns a wind turbine placed inside a diffuser channel, a solution known as Diffuser Augmented Wind Turbine (DAWT). This type of wind energy converter has recently been an object of numerous studies at the Institute of Turbomachinery of Lodz University of Technology. The examined model sizes included: D_5, D_10, D_20, D_30, D_80 and D_real, where the number states the per cent of test object's cross section area related to the cross-section area of the wind tunnel outlet nozzle supplying air to the test location. The numerical study has been based on a commercial solver ANSYS CFX 15.0, the comparison of the obtained results with available experimental data for D_5, D_30 and D_80 models has been made, leading to the analysis of the results obtained and the conclusions.

The paper discusses results of examination of various wind turbine rotor models implemented in numerical simulations, with particular emphasis on the interaction of a rotor with the surrounding airflow. The study concerns a wind turbine placed at the inlet of a divergent duct, a solution known as Diffuser-Augmented Wind Turbine. This type of wind energy converter has recently been an object of numerous studies at the Institute of Turbomachinery of Lodz University of Technology. The study focuses on the search of wind turbine evaluation method combining high accuracy and tolerable time-to-results factor. The examined models include: FRM (Fully-resolved Rotor Model), ADM (Actuator Disk Model) and authors' modified approach to ALM (Actuator Line Model). The study covers: the implementation of the above mentioned method(s) into a commercial solver ANSYS CFX 15.0, the comparison of the obtained results with available experimental data, the analysis of the results obtained from simulations and the discussion. The paper is characterised by the wide spectrum of actuator models compared with 3D accurate rotor modelling for the estimation of turbine performance, the authors' proposal of the ALM variant, and the comparison of the models also from the viewpoint of the numerical effort (computation time and resources necessary) they require.

Extending the idea of preemptive multitasking to DPRS (Dynamic Partial Reconfiguration Systems) has far-reaching implications as many mechanisms supporting the concept, such as context saving and restoring, have to be built practically from scratch. This paper addresses previously neglected issues, related to design of effective preemption mechanisms for Flip-Flop-based and RAM-based hardware tasks. Furthermore, a very efficient and complete solution to hardware task preemption for Virtex4-based DPRS is presented featuring in bitstream manipulation tool intended for PC and embedded system infrastructure with a DMA-based, instruction-driven reconfiguration/readback controller. Taking advantage of the developed lightweight bus, enhancing management of reconfigurable hardware modules, controller takes care of all essential hardware aspects related to context-switching thereby reducing CPU utilization to necessary minimum.