With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

Embedded power regulators, such as low dropout regulators (LDOs), are generally tested for DC behavior and are rarely characterized dynamically. However, LDO loop dynamics play an important role in the overall behavior of the system. Dynamic characterization of LDOs based directly on LDO specifications requires measurement of output transient response with a step input at various points in the circuit. Such characterization is both difficult and costly. Alternatively, LDOs can be characterized by measuring loop dynamics in the form of a transfer function. Since the system is highly non-linear, transfer function can be characterized around a given operating point in terms of poles and zeros. The stability of the system can be inferred from the loop transfer function. This indirect characterization is more feasible but may result in test escapes. In this paper, we investigate the dynamic LDO characterization by closed loop transfer function and evaluate the test coverage with respect to modeled faults in the circuit. We show that faults that are not detectable with DC tests only become detectable with dynamic testing. We also show that the majority of undetectable faults are redundant with regards to the overall operation in terms of step response.

This paper presents a built-in self-test (BIST) system for Low-Dropout Regulators (LDO). Since the LDO is a closed-loop system, stability is a very important but oft-untested parameter for embedded LDOs. The proposed BIST system can measure stability-related parameters by performing cross correlation between an input pattern mimicking noise in the form of Pseudo Random Binary Sequence (PRBS) and the LDO output. In the proposed BIST system, PRBS is injected at the reference voltage input and a mixed-signal correlator is designed for multiplication and integration at the LDO output. A digital controller is designed to shift the PRBS sequence to enable cross-correlation and generate the required control signals. BIST circuit measures the impulse response in the time domain. LDO stability parameters, such as phase margin, can be calculated based on the impulse response. The proposed LDO BIST and an associated LDO as the design under test (DUT) are designed using GlobalFoundries 40nm process. Post layout simulations are performed in order to verify the functionality and performance of the BIST circuit. Post layout simulations show that the proposed BIST circuit can be used to measure the stability parameter with high accuracy. In addition, the proposed BIST has very low overhead.

Outlier screening is a popular approach employed for automotive product lines. There have been many outlier methods proposed. In practice, it is desirable to choose the “best” outlier method. This work develops a notion of applicability associated with an outlier method on a given set of wafers. A measure for applicability is proposed and experiment results are presented to illustrate its effects for finding outliers and for analyzing customer returns based on data collected from several automotive product lines.

An analytics process is subjective to the perspective of the analyst. This paper presents a learning approach that models the process of how an analyst conducts analytics. The approach is applied in the context of correlation analysis for production yield optimization. The benefit is demonstrated by showing that learning from resolving a yield issue for one automotive product line can help resolve a yield issue for another automotive product line.

Speed binning of system-on-chips (SoCs) using conventional Fmax test requires application of complex functional test patterns. Functional workload-based speed binning techniques incur high test-cost in terms of long test-time and complexity in functional test generation, and require high-end automatic test equipment. In this paper, we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/nearcritical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmaxvalues from a set of randomly tested die during wafer sort. The trained predictor is used to obtain the Fmaxfor the remaining chips. The proposed flow has been demonstrated in an SoC benchmark circuit at 28 nm technology. For sufficient number of training samples, Fmaxis correctly predicted for 99% of the prediction samples.

With silicon technology further scaling, the switching activity is getting more intense in modern designs. The large switching activities together with GHz operation frequency can greatly affect the power integrity by generating IR-drop noises. Excessive IR-drop can cause functional failures such as timing failure, abnormal reset and SRAM flipping. Hence, IR-drop needs to be monitored in-field. However, directly measuring transient IR-drop waveform usually involves high design or equipment cost. This paper presents a low-cost on-chip GHz ring oscillator-based transient IR-drop monitor (TRO). TRO is composed of all-digital elements, and can be easily integrated into existing IC design flow with negligible overhead. Different from traditional transient IR-drop monitors, TRO measures IR-drop waveform width and average in-field, while recovers IR-drop peak, and reconstructs the transient noise waveform during data analysis or customer return, which eliminates the need for custom circuits or high frequency sampling clock. Simulation results show that TRO is sensitive to IR-drop with peak and width larger than 100 mV and 1.0 ns, which is suitable for GHz IC monitoring. The IR-drop noise width detection resolution can reach 0.125 ns and higher under the help of the proposed edge detector, with noise peak and width measurement error rate less than 6.8% and 9.0%, for 97% of the Monte Carlo samples considering process variations. According to the results and analyses, TRO is also able to trigger quick adaptation within one clock cycle.

Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but they are often inefficient and incur unacceptably large area overhead. Our analysis shows that many test points have little or no impact on test coverage. Furthermore, depending on where test points are inserted, they can create a significant area overhead unnecessarily. Therefore, we propose a novel timing-aware framework to evaluate test points' impact on a design, rank them based on their efficiency, and obtain an optimal configuration of the most efficient test points accurately and rapidly. Specifically, the proposed framework considers not only individual test coverage improvement but also area penalty, path timing, and region in which each test point is inserted. Within this framework, we have two metrics, namely, efficient test point insertion (ETPI) and test point removal estimation (TPRE). The ETPI metric is developed to remove the most inefficient test points inserted in the circuit by commercial tools, thereby minimizing area penalty with very limited test coverage loss. The TPRE metric is introduced to estimate area overhead and test coverage for designs with different percentages (number) of test points removed without the actual insertion of test points and without the need for lengthy circuit simulation, thereby quickly selecting the most effective test point removal scheme and saving significant amount of processing time especially for large circuits. Experimental results, collected by applying the metrics to NXP Semiconductors circuits and academic benchmark circuits, indicate that ETPI can reduce area overhead by up to 95% with test coverage loss as low as 0.57%. In addition, results by applying the TPRE metric indicate that the difference between estimation and actual simulation/synthesis results for area overhead is less than 0.20% for most cases, and the difference between them for test coverage is less than 1% for most cases.

In this paper, a novel framework is presented for designing lifetime-reliable SoCs with self-adaptation capability against aging-induced degradation. The proposed flow utilizes the existing logic built-in-self-test (LBIST) hardware, and software implemented machine learning predictor to activate appropriate countermeasures to remedy the wear out in the field. Using an innovative method, we convert ATPG-generated transition delay test patterns into LBIST patterns to activate high-usage critical/near-critical paths in-field, and the corresponding responses are utilized in developing the predictor. A gate-overlap and path-delay-aware algorithm selects the optimum set of patterns. The area and test time overhead for the framework are very low. We implemented our proposed flow on SoC benchmark designs, and the results demonstrated its efficacy.

For 40nm and below technologies, billions of transistors can be integrated into a single chip. Meanwhile, the operation frequency has reached over Giga Hertz. In this case, highly synchronized switching activities can induce significant current, which leads to IR-drop. Excessive IR-drop can cause timing failure, abnormal reset, or disruption of data processing. As a result, dynamic voltage and frequency scaling (DVFS) system implemented effective adaptation strategies are widely used by SoCs to mitigate IR-Drop noise and stabilize performance. As the basis of DVFS action, economic and accurate IR-drop monitors are in great need. This paper presents a novel and efficient IR-Drop Alarmer, which can cooperate with the DVFS system for fast IR-drop adaptation. The IR-drop alarming threshold of the proposed sensor is configurable between 45mV to 120mV. Considering a 1.1ns width IR-drop noise, the IR noise sampling window can be as small as 0.125ns, with alarming duration error rate less than 6.8% for 97% of the Monte Carlo samples considering process variations. Furthermore, the proposed alarmer is composed by all-digital standard gates without an y high frequency sampling clock, which is of low area overhead and power consumption.

In this paper, we present a novel methodology, BIST-RM, to accurately predict the degradation due to aging mechanisms in a SoC at run-time by utilizing the existing LBIST hardware and software implemented Machine Learning classifier. Using an innovative method, we convert ATPG-generated transition delay patterns into LBIST patterns, and the corresponding responses are utilized in developing the predictor. A gate-overlap and path delay-aware pattern selection algorithm selects the features for the classier. Using clock sweeping, LBIST is able to capture the aging effect on targeted paths. The result of machine learning is then utilized to activate countermeasures to remedy the degradation in the field. The area and test time overhead are very low. We implemented our proposed flow on SoC benchmark circuits, and the results demonstrated worst-case prediction accuracy of 94% to 97%.

Probabilistic approaches to the detection of untargeted defects, such as n-detect and standard LBIST (logic built-in-self-test), generally suffer from the need to apply very long test sets to achieve good coverage. However, more targeted approaches that attempt to explicitly model new types of defects, such as cell-aware faults, so that they can be deterministically detected may also lead to unacceptably long test sets. Generally, when tests are applied to circuits that contain scan chains, test results are only captured once the entire pattern has been shifted in and the desired deterministic pattern has been applied. Intervening shift cycles serve only as overhead. This is done because capturing data in the circuit's scan flip-flops during scan shift would destroy the pattern being shifted in. However, if data is captured in shadow flops in a MISR instead, those shift cycles could be used to obtain additional fault coverage. In this paper, we investigate the ability of the intervening shift cycles to achieve high static cell-aware fault coverage using only the test patterns generated to detect stuck-at faults. We also investigate reducing the number of shadow flops required. Our results show that high cell-aware coverage is achievable even when only a stuck-at test set is applied — in some cases equal to the coverage obtained by a dedicated cell-aware test set.

Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test (LBIST) schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but they are often inefficient and incur unacceptably large area overhead. Our analysis shows that many test points have little or no impact on test coverage. Therefore, we propose a framework to evaluate test point's impact on a design and rank them based on their efficiency, and to obtain an optimal configuration of the most efficient test points accurately and rapidly. Within this framework, we have two metrics; namely the efficient test point insertion (ETPI) metric and the test point removal estimation (TPRE) metric. The ETPI metric is developed to remove the most inefficient test points inserted in the circuits by the commercial tools, thereby minimizing area penalty with very limited test coverage loss. The TPRE metric is introduced to quickly select the appropriate test point removal scheme. Since TPRE can estimate area overhead and test coverage for designs with different percentage of test points removed without the actual insertion of test points and without the need for lengthy circuit simulation, large amount of processing time is saved especially for large circuits. Experimental results indicate that ETPI can reduce area overhead reduction by up to 95.00% with test coverage reduction as low as 0.57%. In addition, results by applying the TPRE metric indicate that the difference between estimation and actual simulation/synthesis results for area overhead is less than 0.10% for most cases, and the difference between them for test coverage is less than 1.00% for most cases.

For 45-nm technologies and below, the maximum operation frequency of integrated circuits (ICs) has reached multiple gigahertz. At the same time, the size of modern ICs has increased significantly with several billions of transistors integrated on each die. When a large number of transistors switch at the same time, high current consumption is generated. The high current consumption combining with the parasitic resistance and inductance of the power supply network generates a significant power supply noise peak, which causes abnormal reset and generates excessive radiation emission, and hence needs to be accurately monitored, adapted, and mitigated. This paper presents a novel power supply noise measurement and adaptation system that can monitor the peak power supply noise and make dynamic adaptation within one clock cycle. The proposed system has been implemented in Nangate 45-nm technology. It has been proved that the proposed measurement and the adaptation system can successfully avoid the performance degradation or functional failure due to excessive power supply noise. The peak power supply noise monitoring accuracy is 5 mV. The adaptation reaction time is 75%-100% of single system clock cycle. The proposed system is robust against temperature and process variation, and of negligible area overhead and power consumption.

Speed binning of integrated circuits using Fmax test of a SoC requires application of complex functional and structural test patterns. Today's test-pattern-based speed binning techniques incur high test cost in terms of long test time and requires significant effort to generate effective patterns. In this paper we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/near-critical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmax values from a set of randomly tested die during wafer sort. The proposed flow has been demonstrated in a SoC circuit at 28/32nm technology. The worst-case miss-binning of the predictor is within 6% of the nominal Fmax.

In this work, we study the generalization of an outlier model from two perspectives, temporal and spatial. We show that model generalization with existing distribution-based outlier analysis methods can vary significantly. We then propose a “big data” outlier analysis approach together with a probability-based outlier evaluation for improving model generalization. Experiments are conducted based on two automotive product lines to explain the concepts and demonstrate the effectiveness of the proposed approach.

Because of process variations, the post-silicon critical or near-critical paths differ from those identified in the pre-silicon stage. Thus, it has become necessary to extract timing slack information from circuit paths in the post-silicon phase. In this paper, we present a robust digital sensor IP for in-situ timing slack monitoring on actual circuit paths from SoCs. The timing slack data is converted into a digital format and stored in a dedicated scan register chain for easy extraction at any point in time during test and functional modes. A novel layout-aware and netlist-level sensor insertion flow is proposed. The sensor IP has been designed with 32/28nm standard cell library and its performance is demonstrated in the physical design of several benchmark circuits.

As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and electronic design automation (EDA) industries, which may cause significantly increased mismatch between modeled and actual silicon behavior, and even IC failure in field. Therefore, the addition of accurate and low-cost on-chip sensors is of great value to reduce the mismatch and perform in-field measurements. This paper presents a novel standard-cell-based sensor for reliability analysis of digital ICs (called Radic), in order to better understand the characteristics of gate, functional path aging and process variations' impact on timing performance, and perform in-field aging measurements. The Radic sensor has been fabricated on two floating gate Freescale SoCs in very advanced technology. The measurement results demonstrate that the resolution can be better than 0.1 ps, and the accuracy is kept throughout aging/process variation. Additionally, a built-in aging adaption system based on Radic sensor is proposed to perform in-field aging adaption. Simulation results verify that, comparing with designs with fixed aging guardband, the proposed aging adaption system releases 80% of aging timing margin, saves silicon area by 1.02%-3.16% at most targeting frequencies, and prevents aging induced failure.

Process variations and aging effects are proven to have significant impact on paths delay in integrated circuits as technology continues to scale. Identification of the critical paths to test, in a low-cost manner, during both manufacturing and infield tests is thus a challenging task. In this paper, we propose a methodology for identifying testable representative paths (TRPs). The maximum mean delay and variance of the TRPs closely follow the maximum mean delay and variance of all critical paths in the circuit. TRPs, a small subset of critical paths, are selected using a novel QR decomposition-based algorithm taking into account circuit topology, process variations, and aging effects. Our results show up to 70.87% and 60.77% reduction in total number of critical paths and path delay fault (PDF) patterns, respectively.

High test quality can be achieved through defect oriented testing using analog fault modeling approach. However, this approach is computationally demanding and typically hard to apply to large scale circuits. In this work, we use an improved inductive fault analysis approach to locate potential faults at layout level and calculate the relative probability of each fault. Our proposed method yields actionable results such as fault coverage of each test, potential faults, and probability of each fault. We show that the computational requirement can be significantly reduced by incorporating fault probabilities. These results can be used to improve fault coverage or to improve defect resilience of the circuit.

This work studies the potential of capturing customer returns with models constructed based on multivariate analysis of parametric wafer sort test measurements. In such an analysis, subsets of tests are selected to build models for making pass/fail decisions. Two approaches are considered. A preemptive approach selects correlated tests to construct multivariate test models to screen out outliers. This approach does not rely on known customer returns. In contrast, a reactive approach selects tests relevant to a given customer return and builds an outlier model specific to the return. This model is applied to capture future parts similar to the return. The study is based on test data collected over roughly 16 months of production for a high-quality SoC sold to the automotive market. The data consists of 62 customer returns belonging to 52 lots. The study shows that each approach can capture returns not captured by the other. With both approaches, the study shows that multivariate test analysis can have a significant impact on reducing customer return rates especially during the later period of the production.

As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and EDA industries, since a significantly increased mismatch is emerging between modeled and actual silicon behavior. Therefore, the addition of accurate and low-cost on-chip sensors is of great value to reduce the mismatch. This paper presents a standard-cell-based, novel, and accurate sensor for reliability analysis of digital ICs (Radic), in order to better understand the characteristics of gate/path aging and process variations' impact on timing performance. The Radic sensor performs aging, flip-flop (FF) metastability window and variation measurements on-chip. This sensor has been fabricated in a floating gate Freescale SOC in very advanced technology. The measurement results demonstrate that the resolution is better than 0.1ps, and the accuracy is kept throughout aging/process variation. Furthermore, reliability and FF metastability measurements are performed using the proposed sensor. The measurement results agree with the existing models.

With technology scaling, the deviation between predicted path delay using simulation and actual path delay on silicon increases due to process variation and aging. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive measurement devices. In this paper, a novel path-delay measurement architecture called path-based ring oscillator (Path-RO) which takes into account variations is proposed. Path-RO can perform accurate on-chip path-delay measurement with nearly no impact on functional data path. At the same time, process variations will not affect the measurement accuracy. The accuracy degradation due to aging is also negligible, which enables Path-RO to monitor path delay throughout aging process. This delay sensor is perfectly suitable for fast and accurate speed binning as well. By targeting speed paths, the speed of chip can be binned efficiently even in presence of clock skew. Various simulation results collected by Path-RO inserted into b19 circuit demonstrate its high accuracy and efficiency.

Aging of transistors has become a major reliability concern especially when the VLSI circuits are in the nanometer regime. In this paper, we propose a novel methodology to address circuit aging in the field. On-chip aging sensor is designed to monitor transitions on functional paths capturing functional mode workload. Path delay is then accurately measured and converted to a digital value. Diagnosis and calibration are performed in the field, thereby achieving power-performance optimization throughout the entire lifetime. Simulation results demonstrate the efficiency of the proposed structure.

This work proposes a wafer probe parametric test set optimization method for predicting dies which are likely to fail in the field based on known in-field or final test fails. Large volumes of wafer probe data across 5 lots and hundreds of parametric measurements are optimized to find test sets that help predict actually observed test escapes and final test failures. Simple rules are generated to explain how test limits can be tightened in wafer probe to prevent test escapes and final test fails with minimal overkill. The proposed method is evaluated on wafer probe data from a current automotive IC with near zero DPPM requirements resulting in improved test quality and reduced test cost.

Testing for small-delay defects (SDDs) becomes necessary as technology further scales. Traditional timing-unaware transition-delay fault (TDF) ATPGs are not adequate for detecting SDDs due to sensitization of short paths. Timing-aware ATPGs suffer from multiple paths sensitization limitation and significant test cost. In this paper, we present a critical fault-based methodology to generate high-quality SDD patterns. By focusing on critical faults, high quality original pattern repository could be generated applicably with n-detect ATPG. Novel pattern evaluation and selection method is presented to further minimize pattern count while maintaining the SDD detection ability. Finally, top-off ATPG is performed to ensure meeting the target fault coverage. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5X and saves approximately 80% CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, our pattern set detects equivalent or even more SDDs with significantly reduced pattern count.

This paper studies the potential of using wafer probe tests to predict the outcome of future tests. The study is carried out using test data based on an SoC design for the automotive market. Given a set of known failing parts, there are two possible approaches to learn. First a single binary classification model can be learned to model all failing parts. We show that this approach can be effective if the failing parts are compatible in learning. Second, an individual outlier model can be learned for each failing part. We show that this approach is suitable for learning failing parts such as customer returns, where each may have a unique failing behavior. We also show that with Principal Component Analysis (PCA), a learning model can be visualized in two or three dimensional PC space, which facilitates an engineer to manually select or adjust the model.

Semiconductor industry has come to the era to rely heavily on detecting small-delay defects (SDDs) for high defect coverage of manufactured digital circuits and low defective parts per million (DPPM). Traditional timing-unaware transition-delay fault (TDF) ATPGs are proven to be inefficient in detecting SDDs. The commercial timing-aware ATPGs have been developed for screening SDDs, but they suffer from large pattern count and CPU runtime. The previously proposed methodologies are either inefficient or too complex in terms of memory and runtime to be applied to large industry designs (

Customer returns are defective parts that pass all functional and parametric tests, but fail in the field. To prevent customer returns, this paper analyzes wafer probe test data and tries to understand what it takes to screen them out during testing. Because these parts pass all tests, analyzing their signatures based on the original test perspective does not make sense. In this work, we search for a novel test perspective where the test signatures from parametric measurements can be used to separate the returned parts from the rest of population. Our study shows that in order to effectively screen customer returns during wafer test, a multivariate screening methodology is desired. This study is based on analyzing over 1000 parametric wafer probe tests and dies from seven lots, each lot containing one returned part. We demonstrate that analyzing customer returns from a multivariate test perspective leads to robust and conservative results.

Power dissipation of an LSI circuit during scan testing, especially at-speed scan testing, can be several times higher than that during functional operations. Excessive test power causes hot spots and/or severe IR drop that may lead to chip damage, undue yield loss, or reliability degradation, especially for low-power LSI circuits. As a result, it is becoming increasingly important to reduce test power by lowering test-induced toggle activity in order to make scan test “power-safe”. However, with the stress on reducing toggle activity during scan test one might question: Have we gone too far? Should we reduce toggle activity below functional levels? Should we even plan for many test sets with different toggle activities? Can the test power problem be solved by existing DFT and ATPG solutions? What's missing in today's solutions? What's next for low-power testing? This panel provides an interactive forum to discuss these critical questions with industry experts from both semiconductor and EDA companies. It helps practitioners and researchers alike in their quest for more effective and more efficient solutions to the test power problem.

The goal of this hot topic session is to discuss this cutting-edge topic that is being researched by several teams in both academia and industry, and debate which is the best approach for sub-65nm silicon designs. The point of debate will be what embedded circuits make the most sense (aging, enablement of more aggressive design, characterization, diagnosis, debug, etc.).

One of the common failures found in manufactured ICs are interconnect opens. While stuck-at and transition fault automatic test pattern generation (ATPG) patterns can detect open defects, these fault models do not catch all of them. This poster describes a project and research with a new open fault model to supplement the others. The project consists of many parts that target specific types of known open defects.

Is outsourcing DFT implementation possible? Yes, but it takes a lot of up-front work, careful monitoring, and, most importantly, the establishment of a close partnership with your DFT contractor.