Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC'2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.

The current growth of micro-semiconductor technologies requires that an effective solution be found to address the yield and reliability issues associated with embedded memories. A common solution is built-in redundancy analysis (BIRA), which is utilized to guarantee reasonable memory yields. The most common form of BIRA is a module that stores and analyzes fault addresses with a 2-D spare architecture. When the performance of BIRA is evaluated, numerous different parameters are considered, such as repair rate, area overhead, and analysis speed. Because there is a tradeoff between these criteria, many BIRA approaches have been studied so that an ideal BIRA can be found. A novel BIRA approach that focuses on a 100% repair rate and a minimal area overhead is proposed in this paper. In the fault collection phase, the proposed BIRA stores only the essential part of fault addresses in content addressable memories (CAMs), with the rest of the fault addresses being stored in spare memories. After the fault collection phase, a redundancy analysis procedure is performed with the minimum amount of fault information that is stored in the proposed CAM structure. By doing so, the proposed BIRA algorithm can repair all repairable faulty memories while maintaining a minimal area overhead. Our experimental results confirm that the proposed approach exhibits outstanding performance for area overhead, especially when compared to other BIRA approaches that have 100% repair rates.

Advances in memory density and capacity have had the consequence of increasing the probability of memory faults. For this reason, redundancy analysis (RA) and repair are used as effective solutions to improve memory yield. However, as the growth of the number of memory cells increases, it causes increase of the number of faulty cells and results in increase of difficulty of fault analysis. Although various RA methodologies have been proposed, most of them require a long analysis time or fast analysis speed without achieving a 100% normalized repair rate. Furthermore, research on conventional RA methodologies has not included effective early termination methods. Therefore, in this paper, fault group pattern matching (FGPM) is proposed for high speed RA with an effective early termination method. It can achieve very fast analysis with a 100% normalized repair rate. Additionally, it can finish the analysis rapidly by the proposed early termination method when a memory cannot be repaired. Experimental results demonstrate that the FGPM is highly effective in reducing analysis time with the achievement of a 100% normalized repair rate. In addition, the effectiveness of the proposed early termination is shown.

Built-in redundancy analysis (BIRA) is widely used for memory yield improvement. However, increases in fault occurrence probability inevitably lead to the use of various spare lines to achieve a high repair rate. Generally, it is difficult to apply conventional BIRAs for memories with various spare lines because they focus on a simple spare structure. Therefore, this study examines a BIRA that focuses on a various spare lines structure. The proposed BIRA achieves a high repair rate through the use of various spare lines. Although long analysis time is typically required due to the use of various spare lines, the proposed BIRA solves the problem through sequential spare line allocation. Additionally, it achieves hardware overhead reduction through a simple analyzer. These advantages of the proposed BIRA are demonstrated experimentally.

Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy analysis (BIRA) is of utmost importance because the probability of fault occurrence increases with a larger memory capacity. A traditional spare structure that consists of simple rows and columns is somewhat inadequate for multiple memory blocks BIRA because the hardware overhead and spare allocation efficiency are degraded. The proposed BIRA uses various types of spares and can achieve a higher yield than a simple row and column spare structure. Herein, we propose a BIRA that can achieve an optimal repair rate using various spare types. The proposed analyzer can exhaustively search not only row and column spare types but also global and local spare types. In addition, this paper proposes a fault-storing content-addressable memory (CAM) structure. The proposed CAM is small and collects faults efficiently. The experimental results show a high repair rate with a small hardware overhead and a short analysis time.

The limits of technology scaling for smaller chip size, higher performance, and lower power consumption are being reached. For this reason, the memory semiconductor industry is searching for new technology. 3-D stacked memory using through-silicon via (TSV) has been considered as a promising solution for overcoming this challenge. However, to guarantee quality and yield for mass production of 3-D stacked memories, effective test techniques for TSV are required. In this paper, a new test architecture for testing TSVs in 3-D stacked memories is proposed. By comparing voltage changes generated due to resistive open defects with a reference voltage applied externally, the test circuit estimates delay across the TSV. This allows the possibility of a delay test with low-frequency test equipment. Experimental results demonstrate that the proposed test architecture can be effective in the testing of TSV with resistive open defects, and have lower area overhead and lower peak current consumption.

Three-dimensional (3-D) memories using through-silicon-vias (TSVs) as vertical buses across memory layers has regarded as one of 3-D integrated circuits (ICs) technology. The memory dies to stack together in a 3-D memory are selected by a die selection method. In order to improve yield of 3-D memories, redundancy sharing between inter-die using TSVs is an effective strategy. With the redundancy sharing strategy, the bad memory dies can become good 3-D memories through matching the good memory dies. To support die selection and matching efficiently, a novel redundancy analysis (RA) algorithm, which considers various repair solutions, is proposed. Because the repair solutions can be various, the proposed die selection and matching is performed with two stages; general die selection and matching method in the first stage and re-matched remained memory dies, after the first stage, applying other repair solutions in the second stage. Thus, the proposed die selection and matching algorithm using the proposed RA algorithm can improve yield of 3-D memories. The experimental results show that the proposed die selection and matching method can achieve higher yield of 3-D memories than that of the previous state-of-the-art the die selection and matching methods.