As increasing gap of the shrinking ratio between device and metal pitches under advanced nodes, power-grid (PG) structure plays a critical role in circuit performance considering power integrity. Initial PG structures, as initiating implementation fundamentals, dominate optimization space. To address initial structures on industrial flow, we propose the first unified framework fueled by novel sequence-based structure generator and Transformer-based predictor, providing accurate static voltage-drop estimation. Learned embeddings are then adopted to determine promising candidates with Pareto frontier during structure optimization. The predictor is demonstrated in different scenarios under 3 nm and 2 nm technology with average 0.011% maximum absolute error of drop percentage while the optimized structures reduce 15% PG utilization with 34% worst timing-slack improvement on industrial designs.

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits.

This paper presents a novel test generation technique for defective power TSV induced path delay faults in 3D IC. This paper provides a simple close-form analysis to show that, in a regular 3D power grid model, open defects in power TSV do not induce serious IR drop. However, leakage defects in power TSV should be tested, even though the number of power TSV is large. This paper proposes a test generation flow to detect path delay faults induced by defective power TSV. The proposed technique is demonstrated on an 18-tier, 7 x 7 multi-core 3D IC model. In the experiment of b18 and b19 benchmark circuits, all detectable path delay faults induced by power TSV can be tested by around hundred test patterns. This technique requires no extra DfT hardware overhead.