This paper analyses the sensitivity of the pMOS Wheatstone bridge stress sensors in 180-nm CMOS process. Other reported works use coarser process nodes. The pMOS sensors have a maximum or minimum sensitivity to the in-plane normal stress components for different orientations of the bridge arms with respect to the wafer coordinate system. The experimental results show that the sensors oriented orthogonally to the wafer axes have an absolute sensitivity of around 400 µV/MPa, while the absolute sensitivity of the diagonally oriented sensors is around 3 µV/MPa. The temperature measurements show low temperature dependency. The sensitivity to stress changes around −3% at 5 °C and around +1% at 50 °C, with respect to 25 °C.

This paper presents a stress-dependent MOSFET model which is valid from strong to weak inversion, based on the extension of the previous model that covers only the operation in strong inversion. The presented model operates for any MOSFET model type since it does not depend on model parameters. It can be used to simulate complex circuits and compensate for the effects caused by mechanical stress. Mechanical stress is caused by IC packaging and can potentially bring the circuits out of specifications, but stress-aware device models are not standard in circuit simulators which limits the ability to simulate these effects. A measurement method is presented and used to calibrate and validate the models.

In this work, the design methodology of the relaxation oscillator with the post-processing trimming option for frequency and temperature coefficient is presented. A novel oscillator core is introduced, which ensures good control linearity and insensitivity to CMOS variations of the output frequency as a prerequisite for frequency and temperature calibration. The proposed oscillator operates at 2 MHz and consumes typically about$I_{DD}=97.8\,\,\mu \text{A}$at the nominal temperature of 42.5°C and nominal supply voltage of$V_{DD}=1.8$V. The oscillator is verified experimentally with 10 samples manufactured in 180 nm CMOS process, each covering an area of 0.075 mm2. The frequency and temperature calibration was performed based on the two-point temperature measurements, resulting in a significant improvement in frequency stability. The temperature calibrated oscillator has a temperature variation ±0.30% in the temperature range from −40°C to 125°C, and the variation with the power supply ±0.07% in the supply range from 1.62 V to 1.98 V.

An improved relaxation oscillator core is designed and fabricated in 0.35-μm CMOS process, occupying the area of 0.032 mm2and consuming around 160 μW while running at 1 MHz. Employing a self-compensating chopped comparator structure, the designed oscillator exhibits the improvement in the frequency stability, at the same time retaining a fast start-up and having a minimal overhead in the power consumption and area. Measured on 9 test chips, the frequency variation against temperature is ±0.26% in the temperature range from -40 to 125 °C, and the line sensitivity is 0.16 %/V with the supply voltage changing from 3.0 to 4.5 V.

Modern high reliability EEPROM technologies use advanced screening methods to screen out weak bit cells. In combination with standard ECC (Error Correction Code) methods EEPROMs can be produced to withstand more than 50k endurance cycles at 150°C and have a data retention of 10 years at 150°C. Both the number of endurance cycles and the data retention define the lifetime of an EEPROM memory. After successfully passing the standard EEPROM screening tests only randomly distributed intrinsic failures will be activated during the EEPROM's lifetime. This work will present a highly advanced screening procedure in combination with an area efficient byte replacement strategy that enables an increase in the number of endurance cycles by a factor of 2.5 while the increase in area of the EEPROM memory plane is only 5%.

This paper presents the optimization of an existing electrically eraseable programmable read-only memory (EEPROM) production test flow by means of thorough analysis of the faulty dice and the test flow, which leads to an increase in the yield, a significant decrease in test time, and a decrease in the dppm (increase in quality) level leaving the factory. In order to manufacture high quality and cost-effective EEPROMs suitable for automotive underhood applications, several topics must be taken into account. In addition to a high reliability EEPROM technology, the choice of an advanced memory architecture including error correction code and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production test flow must not only be able to screen out weaknesses in the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides, which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time-consuming.

We describe a framework for characterizing systematic variations and failures through exploring the hidden patterns of test data from multiple test stages. The framework provides prediction of process variations with a fine resolution based on a limited number of probed process parameters. An unsupervised biclustering technique is then utilized to extract grayscale and binary spatial patterns from process parameters and production test results, respectively, through analyzing both item-to-item and die-to-die correlations in subsets of the test data. A template matching technique exploits these spatial patterns to discover connections between process variations and failures detected by production tests. The proposed framework has been verified by an industrial test dataset of a non-volatile memory product. The discovery of comprehensible correlations between process parameters and some production test items was confirmed by the engineers who have insights to the test dataset.

In order to manufacture high quality and cost effective EEPROMs suitable for automotive under-hood applications several topics must be taken into account. As well as a high reliability EEPROM technology the choice of an advanced memory architecture including ECC and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production testflow must not only be able to screen out weaknesses of the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time consuming. This work will present an optimization of an existing EEPROM production testflow by means of thorough analysis of the faulty dice and the testflow leading to an increase of the yield without reducing quality.

This paper is about how an EEPROM characterization test program for the automotive market was developed for an initial IP Block, introduced into production and then cost and yield optimized for high volume production without risk to quality or reliability.