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N. M. Siva Mangai

dblp:140/1251 · also N. M. Sivamangai · DBLP profile ↗
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5ranked-venue papers
0as first author
4since 2021 · last 2023
0000-0003-4095-0759ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 since 2021
YearPublicationVenuePosition
2023 Design of INV/BUFF Logic Locking For Enhancing the Hardware Security
Naveenkumar R, N. M. Siva Mangai, Napolean A, S. Sridevi Sathya Priya, S. V. Ashika
 J. Electron. Test.2
2022 Hardware Obfuscation for IP Protection of DSP Applications
Naveenkumar R, N. M. Siva Mangai, Napolean A, G. Akashraj Nissi
 J. Electron. Test.2
2022 Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications
Naveenkumar R, N. M. Siva Mangai, Napolean A, S. Sridevi Sathya Priya
 J. Electron. Test.2
2021 A broadband MVDR beamforming core for ultrasound imaging
Jayaraj U. Kidav, N. M. Siva Mangai, Perumal M. Pillai, Sreejeesh S. G.
 Integr.2
2019 An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM
Princy P, N. M. Siva Mangai
 J. Electron. Test.2