The work presents a concept of an implementation of an explainable artificial intelligence (XAI) using effective models of third-generation neurons. The article discusses a concept of building a neural network based on spiking neurons modelled on ladder nervous systems. A distinction is made between voltage signals encoding information in a network and current signals which contain the correlation between information in the network and pattern features. Analyzes feature a neuron model based on the cusp catastrophe theory eliminating network sensitivity to problems of synapse plasticity, weight mismatch and coupling of neurons based on electric models. The paper presents applications of a spiking neural network for reporting the state of water quality while generating justifications. The article contains results of an analysis of confusion of justifications with ACC = 1 for a set of 10,000 patterns. It also discusses the speed of pattern analysis in the simulated network.

Abstract This work addresses monitoring vesicle fusions occurring during the exocytosis process, which is the main way of intercellular communication. Certain vesicle behaviors may also indicate certain precancerous conditions in cells. For this purpose we designed a system able to detect two main types of exocytosis: a full fusion and a kiss-and-run fusion, based on data from multiple amperometric sensors at once. It uses many instances of small perceptron neural networks in a massively parallel manner and runs on Jetson TX2 platform, which uses a GPU for parallel processing. Based on performed benchmarking, approximately 140,000 sensors can be processed in real time within the sensor sampling period equal to 10 ms and an accuracy of 99 $$\%$$ % . The work includes an analysis of the system performance with varying neural network sizes, input data sizes, and sampling periods of fusion signals.

The study demonstrates original environment for synthesizing and implementing current-mode analog circuits in the field programmable analog array (FPAA) technology. The described approach is inspired by existing solutions for digital circuits, implemented using a field programmable gate array. The tools are compatible with the existing hardware architecture description standards (VHDL-AMS, HSPICE) and the existing electronic design automation software. The functionality of the system was divided into a synthesis stage (independent on the hardware layer) and an implementation stage (dedicated to an FPAA platform chosen by the user). This article presents parasitics oriented place&route algorithms of the original system and a method for calibrating the analog part. The tools are also equipped with the option of debugging a programmed circuit. The author presents the functionality of the system with an example of an implementation of a 5th order filter pair and a 35-18-26 perceptron with a balanced structure. The summary is an analysis of the complexity of the implemented algorithms and the measurement of program run-times.