This article proposes a Bayesian learning driven automated embedded memory design methodology that aims to minimize leakage current, minimize power, and maximize performance while meeting predefined constraints. To achieve this objective effectively, we present an automatic tool that leverages a reference initial circuit design to generate a diverse set of schematic and layout options for logic-equivalent circuit variants and various transistor threshold voltage (Vth) modifications, while ensuring compliance with design rules. Subsequently, leveraging the range of circuit options generated, Bayesian optimization is employed not only to identify optimal circuit parameters but also to select the most appropriate circuit topology and individual transistor$V_{th}$to attain the desired design objectives. TSMC 28 nm process simulation results demonstrate the proposed methodology reducing power by 26.28%–46.44%,$T_{\mathrm { access}}$by 25.60%–42.29%, and leakage current by 22.73%–50.11% compared to the compiler-generated design, with a runtime of 10–40 h.

In this paper, we present a Bayesian Optimization (BO)-based methodology for optimizing SRAM design across various configurations while meeting stringent constraints in different Process, Supply voltage, and Temperature (PVT) corners. Our method automatically extracts critical design parameters for power reduction and accelerates optimization using a BO-based approach that suggests multiple points. Additionally, our method efficiently identifies the worst PVT corners, minimizing the number of simulations by considering constraints and utilizing cubic spline interpolation to simultaneously provide optimal circuits for various size instances. By applying our approach, we achieved a significant reduction in dynamic power by 10.24% to 28.55%, access time by 1.76% to 38.16%, and cycle time by 1.20% to 27.39% across all corners while satisfying all constraints. Additionally, assuming our approach is used to optimize all size instances that can be generated by a commercial compiler, the required runtime is reduced by 96.65% to 99.87% compared to using conventional Bayesian Optimization.

This article presents an efficient yield estimation method for the compensated-most probable failure point (C-MPFP) with the probability density function (PDF) estimation. Bayesian optimization (BO) is used to estimate the PDF. The computational cost can be significantly reduced using this method, while maintaining the accuracy. Our experimental results demonstrate that the proposed yield estimation method can reduce the simulation time by more than 20 times compared with the Brute force Monte Carlo (BMC). In addition, the BO-based automated static random-access memory read access design optimization method is proposed. The optimized design found by the proposed method demonstrates a 10% faster speed than arbitrarily selected designs while satisfying the target yield constraint. Consequently, the proposed design optimization process can efficiently reduce the computational cost of yield estimation for a given design as well as effectively reducing the number of times yield estimation is invoked with BO.

This paper presents SRAM design methodology that aims to minimize power consumption and/or maximize performance while meeting predefined constraints through Bayesian optimization (BO). The BO process utilizes sigmoid utility functions to consider the constraints. It also uses a power and performance prediction model based on linear regression, as well as a Gaussian process model accumulation to enable efficient optimization of SRAMs with arbitrary capacity. Moreover, the implementation of automatic layout adjustment enables fully automated optimization without requiring manual layout modifications, allowing for more accurate and efficient optimization process that based on post-layout simulations. Simulation results of TSMC 28nm process show that the proposed methodology reduces 6.9%-17.9% of dynamic power and 0.3%–20.3% of access time compared to the design generated by the commercial compiler. Simulation result spend 10–40 hours and there is no compromising other circuit performance metrics.

In low supply voltage ($\text{V}_{\mathrm {DD}}$), the wordline (WL) underdrive read assist and the negative bitline (NBL) write assist circuits are widely used for stable operation of SRAM. However, NBL consumes enormous energy and WL underdrive read assist degrades performance. A voltage-boosted fail-detecting circuit for selective write assist (VBFD-SWA) and selective cell current boosting (VBFD-SCCB) is proposed for high-density low-power FinFET static RAM (SRAM). VBFD-SWA detects the bitline status and then selectively triggers NBL only when a write failure is detected, reducing the write energy consumption. VBFD-SCCB detects slow bitcell and selectively triggers cell current boosting to improve read performance. The simulation results show that the write energy consumption is improved by 19% and the read performance is improved by 36% by applying the VBFD-SWA and VBFD-SCCB, respectively, with an area overhead of 10%.

In this brief, an energy-efficient, wide-range level shifter (LS) with a logic error detection circuit (LEDC) is proposed. The proposed LS is designed based on a current mirror-based LS (CMLS), and a feedback pFET is added to solve the static current, which is a limitation of the CMLS. Similarly, Wilson’s CMLS (WCMLS) solves the problem of the CMLS through the feedback pFET; however, it cannot convert low supply voltage ($V_{\mathrm {DDL}}$) to high supply voltage ($V_{\mathrm {DDH}}$) fully due to the feedback pFET. In contrast, the proposed LS can convert$V_{\mathrm {DDL}}$to full$V_{\mathrm {DDH}}$using the LEDC. To verify the performance between the proposed LS and the previously proposed LS, the postlayout simulation was performed using the 7-nm finFET model. The simulation results of the proposed LS show that the propagation delay and energy are 0.21 ns and 20.43 fJ, respectively, at a low/high voltage of 0.4/1.2 V and an input frequency of 1 MHz.

In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master–slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at $V_{\mathrm {DD}} =0.4$ and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at $V_{\mathrm {DD}} =0.4$ and 1.0 V, respectively, in comparison with the conventional pulsed latch.

A novel high-speed and highly reliable sense-amplifier-based flip-flop with transition completion detection (SAFF-TCD) is proposed for low supply voltage (VDD) operation. The SAFF-TCD adopts the internally generated detection signal to indicate the completion of sense-amplifier stage transition. The detection signal gates the pull-down path of the sense-amplifier stage and the slave latch, thus overcoming the operational yield degradation, current contention, and glitches of previous SAFFs. The operational yield, speed, hold time, energy consumption, and area of the proposed and previous FFs are quantitatively compared for a wide range of VDDwith 22-nm FinFET technology. It is shown that the minimum VDDof the SAFF-TCD is 573 mV lower than that of previous SAFFs, which means the SAFF-TCD can operate even when VDDis in the near-threshold or subthreshold region. At 0.3-0.4 V, the SAFF-TCD operates twice as fast as the master-slave-based FF (MSFF) with a practical hold time. Even with these benefits, the energy consumption overhead is limited to less than 20% compared with that of MSFF, and the area is similar to that of previous SAFFs.

This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual VSS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6σ read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.

The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, because it degrades the read stability of the SRAM. Thus, a full-swing local BL cannot be achieved, and the gate of the read buffer cannot be driven by the full supply voltage (VDD), resulting in a considerably large read delay. To overcome the above disadvantage, in this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full VDD, without the need for the boosted WL voltage. Various configurations of the proposed SRAM architecture, which stores multiple bits, are analyzed in terms of the minimum operating voltage and area per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology.

A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and ac-coupled sensing schemes, respectively. Further, compared with the ac-coupled sensing scheme, the proposed scheme offers 10% lower sensing power, 36% lesser area, and a 60 mV lower value of the minimum supply voltage for the target sensing yield.

We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient.

In this paper, we propose a method to estimate the read failure rate of a static random access memory (SRAM) cell. Conventional read stability metrics cannot accurately estimate the read failure probability as technology scales down, because some metrics cannot characterize read stability and others can no longer be approximated to a known distribution. We first introduce a one-sided static noise margin (OSNM), whose lower tail region follows a Gaussian distribution, and also propose a Gaussian-tail-fitting method that properly models the distribution of the OSNM at the tail region. It is demonstrated that the OSNM can accurately estimate the SRAM cell yield using the proposed Gaussian-tail-fitting method.

When the input voltage difference of a sense amplifier (SA) exceeds the offset voltage (VOS), the SA correctly detects it and outputs a large signal. However, when the input voltage is in a certain region, the SA can fail to sense the input voltage difference even if it is sufficiently large. This input voltage region is defined as the sensing dead zone of the SA. Because sensing dead zones differ depending on SAs and the input voltages to the SA differ depending on the memory devices, analyzing the sensing dead zone is very important. In this brief, we analyze the sensing dead zones of the most popular latch-type SAs: voltage- and current-latched SAs. Furthermore, a suitable latch-type SA scheme is suggested for various SA input voltages in terms of sensing delay, power consumption, and PDP, using a 65-nm predictive technology model at a VDD of 1.1 V.