In this paper, a rapid binary search-based calibration method for capacitor mismatch errors in CDAC structures is proposed. Limitations of existing methods, such as the need for ADC architecture modifications, long convergence times, and high design complexity, are addressed by this approach. By employing a simple binary search algorithm, capacitor weights are quickly optimized to maximize the SNDR, effectively calibrating capacitor mismatch errors. The implementation of this method is relatively straightforward, with comparatively low computational resource requirements, offering strong flexibility. Simulation results for a 14-bit Pipelined-SAR ADC model indicate that, after calibration, average SNDR and SFDR improvements of 8.74 dB and 20.65 dB, respectively, were achieved.

This paper presents a reconfigurable 4.75-to-32 GBuad transmitter (TX) that operates up to 64Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 32Gb/s with non-return-to-zero (NRZ) modulation scheme, designed in the 28-nm CMOS technology. The TX incorporates a quarter-rate architecture with a tap coefficient flexible feed-forward equalizer (FFE) up to 3 FFE taps. The TX employs a tailless CML driver with common-mode feedback (CMFB) for output swing control which provides 0.8 V pp output swing, and a helical wiring T -coil for bandwidth expansion. The clock path of the TX includes the duty-cycle detection/correction (DCD/DCC) circuits with a resolution of sub-60fs and quadrature-error detection/correction (QED/QEC) circuits, and a LC phase locked loop (PLL) with a local injection-locked (IL) quadrature clock generation circuit. The TX operating at 64 Gb/s in PAM-4 modulation consumes 76.7 mW from 1-V supply with 0.8 V pp, achieving an 1.2 pJ/b energy efficiency. The TX front end occupies an active area of 0.063 mm2.

This paper presents a foreground calibration technique with LSB capacitors for an 18-bit SAR ADC. Calibration using LSB capacitors suffers from poor accuracy owing to the comparator static offset and the random mismatch in LSB capacitors. The proposed floating capacitors operation addresses the miscalibration due to the saturation of sub-ADC resulting from the static offset. In addition, calibration using multiple groups of LSB capacitors is taken for each capacitor measurement to average out the effect of random mismatch in LSB capacitors, which improves the calibration accuracy effectively. Behavioral simulations of an 18-bit SAR ADC demonstrate the availability and robustness of the proposed calibration techniques.

In this paper, a novel foreground calibration method for wideband zero IF receiver I/Q mismatch is proposed based on frequency domain feature extraction, which is suitable for the FDD transceiver integrated with digital signal processing modules. The proposed algorithm calibrates the frequency dependent mismatch through a complex digital FIR filter, and uses the transmitter as the signal source. A frequency allocation scheme is applied to avoid the interference from the transmitter image component. Mismatch factors such as LO phase and amplitude mismatch and baseband transfer function mismatch can be calibrated together directly by this method, which eliminates the error accumulation caused by multi-level cascade calibration. Finally, a high image rejection ratio is obtained, and the image component power is stably compressed below the quantization noise power in the whole baseband.

This paper first analyzes the delay and energy consumption mechanism of SMAC. Then it proposes an improved DC-SMAC protocol by replacing the fixed duty mechanism with adaptive duty cycle mechanism, which adopts a priority discriminant function to make the node with more packets have the priority to access channel. The simulation results show that the proposed adaptive duty cycle mechanism can effectively reduce the network delay, increase the network throughput, improve energy efficiency of the node, and effectively enhance the network performance in the coordination with contention window adjustment mechanism.