This paper introduces an innovative data-driven approach to uncertainty quantification (UQ) in complex engineering designs based on polynomial chaos expansion (PCE) and least-square support-vector machine (LSSVM). While PCE is a prevalent UQ method, its reliance on a predefined model form poses limitations in the model complexity, training accuracy, and efficiency in high-dimensional settings. To overcome this, we propose a nonparametric reformulation that draws equivalence with the kernel-based LSSVM. Leveraging special implicit kernels based on Hermite or Legendre polynomials, our method achieves accurate predictions with reduced training data. The model is trained through the dual space LSSVM formulation, thereby exploiting the so-called “kernel trick”, while PCE coefficients up to an arbitrary order are efficiently obtained post-training. Validation encompasses a diverse range of scenarios, including standard benchmarks and real-life applications in electrical engineering involving up to 26 independent random input parameters. The proposed “PCE-LSSVM” method exhibits superior performance over traditional PCE implementations. It achieves up to 7 times smaller root-mean-square error and up to 10 times lower dispersion across various training datasets, showcasing superior performance even with a significantly reduced number of training samples. Notably, this approach is 2 to 50 times more efficient compared to alternative approaches such as ordinary least square regression or Gaussian quadratures. Overall, PCE-LSSVM emerges as a powerful and efficient tool for accurate UQ in complex engineering systems.

This article introduces a probabilistic machine learning framework for the uncertainty quantification (UQ) of electronic circuits based on the Gaussian process regression (GPR). As opposed to classical surrogate modeling techniques, GPR inherently provides information on the model uncertainty. The main contribution of this work is twofold. First, it describes how, in a UQ scenario, the model uncertainty can be combined with the uncertainty of the input design parameters to provide confidence bounds for the statistical estimates of the system outputs, such as moments and probability distributions. These confidence bounds allow assessing the accuracy of the predicted statistics. Second, in order to deal with dynamic multioutput systems, principal component analysis (PCA) is effectively employed to compress the time-dependent output variables into a smaller set of components, for which the training of individual GPR models becomes feasible. The uncertainty on the principal components is then propagated back to the original output variables. Several application examples, ranging from a trivial RLC circuit to real-life designs, are used to illustrate and validate the advocated approach.

High-speed communication over mutually coupled channels can be severely affected by intersymbol interference (ISI) and crosstalk (XT). Multiple-input multiple-output (MIMO) equalization is known to mitigate both ISI and XT, but requires accurate channel information at the receiver (RX) and/or transmitter (TX), when the channel is stochastic. However, since adjusting the equalization filters to the specific channel realization involves a considerable implementational and computational complexity, it is desirable to keep the equalization filters fixed irrespective of the specific channel realization, especially when the channel variability is relatively small. Therefore, we propose a general MIMO transceiver scheme where the equalization filters depend on the channel statistics rather than the actual channel. More specifically, by considering the time-domain equalization with the fixed linear MIMO pre-equalization and adjustable MIMO decision feedback equalization, the complexity associated with passing channel information from the RX to the TX is avoided, and the computationally intensive and iterative calculations of the fixed pre-equalizer can be performed offline rather than on-chip. The proposed equalization scheme is shown to yield only a small performance degradation compared to fully adjustable equalization schemes, thereby enabling multi-Gbit/s chip-to-chip communication over low-cost electrical interconnects which are prone to manufacturing tolerances.

While the requirements for delivering high throughputs increase exponentially with every generation of access node hardware, the device cost is of primary concern. As a result, multiple- input multiple-output (MIMO) equalization, which has been shown to facilitate multi-Gbit/s communication over low-cost parallel electrical interconnects, is emerging as an attractive high- speed interconnect solution for next-generation access nodes. Because of the high operating frequencies, however, the transfer functions of the on- and off-chip interconnects become highly susceptible to manufacturing tolerances (MTs); hence, the equalization filters must be adjusted to the specific channel realization to achieve optimal performance, which involves a high implementation and computational complexity. Considering that the MTs are usually limited, we propose a robust low-complexity transceiver consisting of a fixed MIMO linear pre-equalizer (which avoids the need for feeding back the channel state information to the transmitter), with either a fixed or adjustable MIMO decision- feedback equalizer (DFE). For a specific chip-to- chip interconnect operating at 75 Gbit/s per line and a 26 dB signal-to-noise ratio, we show that the resulting bit error rate does not exceed 10^(-12) for MTs up to 10.5% (fixed DFE) and 17.7% (adjustable DFE) of the nominal line width.