Physical Unclonable Functions (PUFs) are a very useful resource in cryptography with many applications ranging from system authentication to secret key generation. Side-channel attacks (SCAs) are a major concern in any physical implementation of a cryptographic module, and PUFs are no exception. Electromagnetic (EM) leakage from the implementation of a ring-oscillator-based PUF (RO-PUF) can be exploited to retrieve sensitive information that compromises the security of the cryptographic scheme incorporating the PUF. In this paper, we analyse the EM leakage of an RO-PUF implemented on FPGA, highlight its main vulnerabilities, and propose alternative countermeasures and architectures to mitigate the threat of this type of attack. Furthermore, we evaluate the cost in terms of area overhead of the proposed implementations compared to the original design.

The development of hardware countermeasures against hardware attacks has attracted the attention of the scientific community over the past two decades. Side-Channel Analysis (SCA) and Fault Injection Attacks (FIA) represent a significant risk to the security of cryptographic circuits. Combined countermeasures against these types of attack must be carefully designed if both protections are required in the same implementation without interfering with the other. In this paper, a combined proposal is presented to counteract the SCA and FIA attacks. SCA countermeasures are based on a low-entropy masking scheme, while the FIA countermeasure is based on a signature generator detection scheme. Both have been experimentally implemented in an AES cipher in FPGA. Experimental FIA attacks, first-order Correlation Power Analysis (CPA) attacks, and Test Vector Leakage Assessment (TVLA) tests have been carried out to evaluate the improvement in the security levels. The experimental results show that for an increase in area 28.77% and a frequency degradation of 4.05% with respect to the unprotected implementation, the protected Advanced Encryption Standard (AES) scheme shows great security metrics against FIA (99.87% fault coverage) and SCA attacks.

Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to minimize this type of vulnerabilities, several mechanisms have been proposed to detect this type of attacks. However, these mechanisms can have a significant cost or not adequately cover the implementations against fault attacks. In this paper a novel approach is proposed, consisting in generating the signatures of the internal state using a Hamming code. This allows to cover a larger amount of faults allowing to detect even or odd bit changes, as well as multi-bit and multi-byte changes, the ones that make ciphers more vulnerable to DFA attacks. As case of study, this approach has been applied to the Advanced Encryption Standard (AES) block cipher implemented on FPGA using T-boxes. The results suggest a higher fault coverage with an overhead of 16% of resource consumption and without any penalty in the frequency degradation.

The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.

In this paper, a Differential Power Analysis (DPA) vulnerability analysis on Trivium stream cipher is presented. Compared to the two previously presented DPA attacks on Trivium, we retrieve the whole key without making any hypothesis during the attack. An optimized power model is proposed allowing the power trace acquisition without making any algorithmic-noise removement thus simplifying the attack strategy considerably. The theoretical vulnerability analysis is presented and then checked developing a simulation-based DPA attack on a standard CMOS Trivium implementation in a 90nm TSMC technology. The results show that our attack is successful for random keys, saving in computer resources and time respecting to previously-reported attacks. The attack is independent on technology used for the implementation of Trivium and can be used to measure the security of novel Trivium implementations.

Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulation based DPA attacks on Sbox9 are used to validate the effectiveness of the proposals.