For the first time, this paper presents an unsupervised learning residual long short-term memory (ULR_LSTM) neural network to develop a digital predistortion (DPD) method for the linearization of digital power amplifiers (DPAs). Our method eliminates the need for iterative learning control (ILC) to obtain the ideal input of the DPA required by state-of-the-arts (SOTAs), which leads to high computational complexity and extensive training time. We perform behavioral modeling of the DPA using the R_LSTM network. After determining the optimal behavioral model architecture, the corresponding DPD model is obtained through an inverse training process. A 15-bit transformer-based quadrature DPA chip incorporating Class-G and IQ-cell-sharing techniques was implemented in a 28nm CMOS process to validate our proposed method. Experimental results demonstrate outstanding linearization performance comparing to prior arts, achieving an error vector magnitude (EVM) of -40.4dB for the 802.11ax 40MHz 64QAM signal.

This paper presents a modified vector combination (MVC) model to analyze the nonlinearity behavior in the quadrature switched-capacitor power amplifier (SCPA), which improves model accuracy while reducing the number of recorded points and iterations compared to the two-dimensional (2-D) LUT-based model. To analyze the nonlinearity caused by efficiency enhancement techniques, high-order Taylor series are applied to meet the model accuracy requirement. Moreover, a two-stage process with MVC and general memory polynomial (GMP) digital predistortion (DPD) is introduced to calibrate the static nonlinearity and memory effect, respectively. In the measurement, a 15-bit transformer-based quadrature SCPA chip with Class-G and IQ-cell-sharing techniques is implemented in 28nm CMOS and employed to verify the effectiveness of the MVC and two-stage DPD methods. For the 802.11ax 40MHz 64QAM signal at 2.4GHz, this chip achieves up to −40.9dB error vector magnitude (EVM) floor and significant EVM improvement even at deep power back-offs after the DPD.

In this paper, a potential threat to reliability of Software Defined Networking (SDN) is disclosed: the cascading failures of controllers. Current SDN designs have widely utilized multiple controllers and the load of a failed controller can be redistributed to the other controllers. However, simply utilizing multiple controllers cannot protect SDN networks from a single point of failure: the load of the controllers which carry the load of the failed controller can exceed the capacity of them, and then cascading failures of controllers will happen. In this article, at first we propose a model for such failures and present simulation results based on the model. Strategies for initial load balance and load redistribution after failure are designed to prevent such failures. The simulation result shows the strategies can significantly increase the resistance of SDN networks to cascading failures.