With advancements in Internet of Things (IoT) technologies for Intelligent Transportation Systems (ITS), gathered vehicle data can provide insights into emerging vehicular phenomena and help the continued enhancement of creative and efficient vehicular systems. Overall, improvements to ITS have had a significant influence on society. Predictive maintenance will discover faults within the vehicle and offer early warnings to avert failure by using data collected from car sensors and maintenance models built from prior vehicle repairs. The primary goal of this study is to develop a secure, privacy-preserving, and continuous data-gathering strategy for predictive maintenance, utilizing a K-Nearest Neighbor (KNN) aggregation over an encrypted data scheme and a Neural Network (NN) prediction model. In this suggested approach, data will be exchanged among vehicles, fog nodes, and a cloud server. The vehicle’s sensors will produce a sensory data report and transmit it to the fog nodes after encryption to preserve the vehicle’s user privacy. The encrypted information will be aggregated through the fog nodes before being transferred to the cloud server. Finally, the cloud server will issue maintenance details to fog nodes and vehicles using an NN predictive model. Furthermore, the proposed scheme’s capability for implementation on hardware is comprehensively examined and evaluated. Our security and privacy evaluation shows that the scheme can achieve our design goals. Additionally, our performance evaluation shows that our scheme has low computation and communication overheads compared with the existing techniques. Especially for the NN-based model that achieves 100% accuracy, 100% precision, 97.5% recall, and 98.7% F1-score through the software tests; at the same time, it performs with good utilization values on the FPGA board.

Drunk driving detection systems are traditionally reactive, relying on tools such as breathalyzers or field sobriety tests deployed only after unsafe behavior is observed. To address this limitation, recent advances in computer vision and deep learning have enabled the development of proactive, non-intrusive systems capable of detecting intoxication based on facial features. This paper expands on our previous work by focusing on out-of-vehicle drunk driving detection, leveraging facial imagery captured from external sources such as roadside cameras or drones. We apply Machine Learning (ML) and Deep Learning (DL) models to a large-scale dataset of sober and intoxicated faces, introducing controlled salt-and-pepper noise at 20%, 40%, and 50% levels, along with disruption techniques such as flipping and brightness variations to simulate real-world surveillance conditions. We proposed two configuration modes, low-resource and high-resource models, to illustrate the applicability of our scheme to devices with different resource constraints. To enhance transparency, we integrate Explainable AI (XAI) tools—such as saliency maps—to identify key facial regions influencing model decisions. In addition to software-based evaluation, this work investigates the feasibility of real-time deployment through a hardware–software co-design implemented on a Field-Programmable Gate Array (FPGA) platform. Both low-resource and high-resource model configurations are analyzed with respect to architectural design and resource utilization, demonstrating the practicality of embedded inference in roadside and edge environments. By supporting efficient edge-level inference, the proposed system is well-suited for Internet-of-Things (IoT) deployments that rely on distributed roadside sensors and embedded processing platforms.

The security of Multi-Processor System-on-Chip (MPSoC) architectures has become a critical concern due to their widespread integration into modern computing systems. However, the lack of quality data capturing the behavior of these systems under attack scenarios hinders the development of effective countermeasures. In this study, we propose a framework that facilitates the collection and enrichment of thermal datasets using machine learning for MPSoC security analysis against two distinct thermal attack patterns. To address the limitations associated with imbalanced data, the proposed framework leverages Large Language Models (LLMs) to generate synthetic data, incorporating a feedback-driven optimization mechanism to enhance data quality and alignment with real-world distributions, we developed a prompt-based LLM pipeline for schema-conformant tabular synthesis and evaluate its downstream utility by training standard off-the-shelf ML models on the generated tables. The framework employs a novel prompting method to ensure compatibility across various LLMs, thereby optimizing the synthetic data generation process. Experimental evaluations provide empirical evidence substantiating the framework’s efficiency in generating and enriching synthetic data for training machine learning models. The experimental evaluation reveals that the Light Gradient Boosting Machine algorithm achieved the best performance among all tested models, attaining an accuracy of 93% and an F1-score of 92.80% when trained only on synthetic data and evaluated on real data. The findings highlight its potential as a powerful tool for strengthening MPSoC security by improving the robustness and adaptability of machine learning-based security mechanisms.

Through-silicon vias (TSVs) are essential for 3D integrated circuits (ICs) and advanced chiplet packaging. The semiconductor industry is transitioning toward 3D ICs, chiplets, and system-in-package (SiP) solutions due to the slowdown of Moore’s Law and limitations in conventional silicon scaling. In this paper, we propose an optimized TSV architecture for high-frequency transmission to enhance its suitability for 6G communication chips, and develop a comprehensive equivalent circuit model for fault-free and faulty TSVs. This model accounts for open-circuit and short-circuit fault conditions while considering the effects of higher frequencies, substrate type, doping concentration, and adjacent layers. At the physical level, the TSVs are simulated using the Ansys High-Frequency Structure Simulator (HFSS), and the equivalent circuits are designed using the Cadence Virtuoso tool. An experimental evaluation is also conducted to validate the physical design. We position the TSVs in a pattern of ground-signal-ground (G-S-G) to reduce the effective inductance of the signal TSV, thereby minimizing inductive reactance at ultra-high frequencies. Consequently, the reflection coefficient remains below -10 dB across the frequency range of 0.1 to 146.3 GHz. Furthermore, we compare simulation outcomes from HFSS and Cadence for both fault-free and faulty TSVs under varying operating conditions. Additionally, the parasitic circuit components are characterized through extensive theoretical derivations for in-depth circuit verification. Collectively, the rigorous analysis, experimental validation, and thorough investigation of the proposed design and its equivalent circuit demonstrate their potential for use in creating datasets for a fault prediction machine learning model.

For over half a century, silicon-based Complementary Metal Oxide Semiconductors (CMOS) have been the dominant technology used in the manufacture of nearly all integrated circuits. To fulfill Moore’s Law prediction, CMOS device dimensions were meticulously and carefully reduced to the single-digit nanometer regime. This gradual reduction has led to remarkable exponential performance increases over several decades, ushering in an unparalleled era of computation in human history. However, Short-Channel Effects (SCEs) present many impediments to further improvements in CMOS devices. SCEs occur when the channel length has been scaled down to the same order of magnitude as the depletion-layer widths of the source and drain junctions. To overcome the numerous SCEs caused by the miniaturization of CMOS devices, Carbon Nanotube Field Effect Transistors (CNFETs) aim to serve as their superior successors. CNFETs exhibit exceptional electrical properties, far surpassing those of CMOS, primarily due to their ballistic transport properties and excellent electrostatic scaling. To the best of our knowledge, this paper is the first to investigate chirality variation in CNFETs for spiking neurons. More specifically, chirality variation in CNFETs is used to determine two optimizations: (1) highest-frequency and (2) lowest-energy spiking neurons, using the Penta-Transistor Integrate & Fire (PTIF) architecture to demonstrate these dual mandates. These optimizations separately provide a 6.89x increase in spiking frequency or an 87.43% energy saving.

This paper presents an efficient Pseudo Random Number Generator (PRNG) design based on a 16-bit Linear Feedback Shift Register (LFSR) with 16 polynomials dynamically controlled by four distinct ring oscillators (ROs). RNGs are the fundamental components of modern digital communications systems. The deterministic properties of PRNGs are used for symmetric key encryption for bulk data transmission and other diverse applications. This work focuses on enhancing the randomness of LFSR-based RNGs to improve security and resource utilization. The proposed method achieves high randomness through dynamic polynomial (taps) selection, providing unpredictability in both sample size and selection. The whole design is synthesized and validated in the Xilinx Vivado 2023.2 tool using a Spartan-7 FPGA board. The randomness quality of the generated bitstream is evaluated using the NIST SP800-22 statistical test suite, with the proposed RNG passing all 16 tests and producing significant P-values. Then, P-values from the NIST tests are compared with the state-of-the-art PRNG methods. In addition, the design performs considerably better with respect to randomness and resource usage than traditional 64-bit Fibonacci LFSR, which did not pass all the NIST tests. The design is also synthesized in the Synopsis design compiler for 14nm, 32nm, and 45nm technology nodes to better understand resource usage. In addition, autocorrelation results are also presented to further validate the quality of generated random numbers. This work provides an efficient, lightweight LFSR-based PRNG architecture for IoT, automation, embedded systems, and symmetric key encryption applications, where high-quality random bits are critical.

Hardware implementation of neural networks (NNs) is challenging due to varying application requirements. This often necessitates creating specific field programmable gate arrays (FPGAs) configurations from scratch for each application. This article proposes a flexible, self-supervised reconfigurable method to fit several application requirements by providing only the maximum available computational nodes a priori. The proposed method dynamically reconfigures the required number of hidden layers and nodes based on the application. The goal is to automatically determine the optimal NN configuration through reconfigurability to achieve maximum accuracy. Optimality is demonstrated through minimum average power, average delay, and area overhead, as well as maximum throughput and accuracy. Experimental results show that the proposed approach significantly reduces the optimized architecture search cost (the number of online training iterations) and associated average power consumption for successive datasets/applications. The method’s effectiveness is shown both quantitatively and qualitatively, verified against the MNIST and CIFAR-10 classification problems. Our reconfigurable method demonstrates stable accuracy of 98.97% and 98.95% compared to state-of-the-art NNs with fixed configurations (98.85% and 73.0% for MNIST and 93.47% and 70.21% for CIFAR-10, respectively). Additionally, the proposed method shows a 20.9% reduction in average power dissipation compared to state-of-the-art methods. Implemented and tested using VHDL and Altera FPGA, the results indicate resource utilization comparable with the state-of-the-art method. This reconfigurability is especially advantageous for Internet of Things applications where power efficiency and adaptability to different tasks are critical.

The Internet of Things (IoT) is a transformative technology facilitating seamless communication between diverse devices and systems, including resource-constrained devices. Speed efficiency and energy efficiency in communication protocols for IoT devices are crucial. The constrained application protocol (CoAP) is a promising, lightweight, and efficient protocol for IoT, offering robust messaging capabilities while conserving resources. An emerging research focus and challenge is designing hardware accelerators for CoAP that are fast, energy-efficient, and reliable. This article addresses that research challenge by proposing a CoAP hardware accelerator for optimizing message processing in resource-constrained IoT environments. The proposed accelerator’s architecture uses virtual channels (VCs) to manage incoming message traffic efficiently, enabling concurrent processing and enhancing throughput capacity. The accelerator minimizes processing delays and improves the system responsiveness by leveraging dynamic resource allocation and streamlined routing mechanisms. The proposed method is implemented using VHDL on Altera 10 GX FPGA. It reduces power consumption by consuming only 112.4 mW. Additionally, the accelerator demonstrates an impressive average latency of$58~\mu $s and energy consumption of$6.62~\mu $J, showcasing its superior performance metrics. The efficacy of the proposed CoAP hardware accelerator is tested through detailed evaluation and comparative analysis, affirming its superior performance over previously reported results in the literature.

Epilepsy triggers seizures, which develop before clinical onset in patients, and a timely and accurate prediction can save lives. A research challenge is to design accurate, fast, and energy-efficient hardware predictors. This work advances hardware-based seizure prediction research by proposing a new machine-learning-based predictor. It proposes a novel reconfigurable electroencephalogram (EEG) signal segmentation for increased learning. The proposed reconfigurable segmentation adaptively adjusts the overlap extent between consecutive segments and prepares new segments. Such prepared segments are fed into a Convolutional Auto-Encoder (CAE) using a proposed convolution module. The proposed convolution module uses optimized hyperparameters, including the number of layers, filters, filter size, pooling method, stride value, and padding for high learning and feature extraction. The learned CAE feeds into an Economic Long Short-Term Memory (ELSTM) to attain the final prediction result. The proposed predictor achieves high accuracy by exploiting the temporal dynamics of epileptic activity. It predicts seizures with an accuracy of 99.32%, a sensitivity of 99.29%, and a false alarm rate of 0.003 per hour, yielding high performance across classification thresholds, incurring low costs, and outperforming related hardware solutions. It is implemented in stand-alone VHDL, Altera Arria 10 GX FPGA, and synthesized into 45-nm technology.

The rapid advancements in nanotechnology and neuromorphic engineering have paved the way for developing high-performance computational models that mimic biological neural networks. This paper presents a novel digital-twin architecture for a spiking neuron, leveraging the exceptional properties of Carbon Nanotube Field Effect Transistors (CNFETs). The proposed architecture aims to emulate the dynamic behavior of biological neurons with high fidelity, providing a robust platform for simulation and analysis. By integrating CNFETs, we achieve significant improvements in lowest-energy usage and highest-spiking frequency, compared to traditional silicon-based technologies. Furthermore, the digital twin not only replicates the electrical characteristics of a spiking neuron but also facilitates advanced functionalities such as adaptive learning, fault tolerance, and self-optimization. Experimental results demonstrate the potential of CNFET-based neurons in enhancing the performance of neuromorphic systems, offering promising applications in artificial intelligence, cognitive computing, and complex system modeling. Integrating digital twin technology with CNFETs allows for precise control and manipulation of spiking behavior, enabling the development of more sophisticated and efficient neural models. This research underscores the transformative impact of combining digital twin technology with cutting-edge nanomaterials, setting a new benchmark for future explorations in the field. The findings highlight the importance of continued research and development in this area, as it holds the promise of revolutionizing the way we design and implement neuromorphic systems, pushing the boundaries of what is possible in artificial intelligence and beyond.

Strong Physical Unclonable Functions (PUFs) have gained traction as lightweight authentication solutions for IoT devices. However, their vulnerability to machine learning attacks poses a security risk. Various strategies have been introduced in the literature to enhance its resilience against modeling attacks, introducing additional complexity and making them unsuitable for resource-constrained devices. In contrast, weak PUFs exhibit inherent resistance to modeling attacks, but they suffer from a restricted number of Challenge-Response Pairs (CRPs), thus unsuitable for authentication. This paper proposes a PUF design that incorporates weak PUFs to obscure the responses of Strong PUFs, effectively safeguarding them from modeling attacks. Our design shows resilience against a modeling attack, revealing a maximum accuracy of 57% despite using 107CRPs. The proposed method is implemented on the Artix-7 FPGA with Verilog HDL. The results demonstrate that the proposed method has a small footprint in terms of resource utilization. This innovative approach offers a lightweight solution for IoT device authentication, combining the strengths of strong and weak PUFs while mitigating the vulnerabilities associated with modeling attacks.

Long Short-Term Memory (LSTM) has become commonly used for problems with a sequence of data. Hardware implementation of LSTM is a challenge for lightweight applications. This paper proposes an optimized LSTM method with few hardware components. The proposed method utilizes one sigmoid function to perform both input and output gates. The proposed method also utilizes one shared adder instead of two adders to perform the accumulation function for both the input and output gates. This unit performs the two functions in a sequence based on a selection signal which is used as a guide. The proposed method is tested using two datasets: MNIST and IMDB. The simulation results show the proposed method achieves the desired performance in classification compared similarly to the traditional method with a few hardware units. The proposed method is implemented using VHDL on Altera Arria 10 GX FPGA. The simulation results show that the proposed method utilizes fewer resources than the traditional method. The proposed method has a 16% area reduction compared to the traditional method. The proposed method has a power consumption of al.546 W while the traditional method consumes 1.847 W. Thus, the proposed method is suitable for lightweight applications with low hardware costs and desired performance.

Convolutional neural network (CNN) hardware accelerators for specialized Internet of Things (IoT) requiring high accuracy is an emerging research topic. The pooling module in a CNN pipeline impacts both the speed and accuracy of a classification task. This work proposes the design and hardware implementation of a novel pooling method absolute average deviation (AAD) for CNN accelerator. AAD utilizes the spatial locality of pixels using vertical and horizontal deviations to achieve higher accuracy, lower area, and lower power consumption than mixed pooling without increasing the computational complexity. AAD is tested on four different datasets: EEG, ImageNet, Common Objects in Context (COCO), United States Postal Service (USPS), and multiple CNN structures: CNN, VGG16, VGG19, ResNet, and DenseNet. In hardware, AAD is implemented using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) on Altera Arria10 GX field-programmable gate array (FPGA) and 45-nm technology using Synopsys Design Compiler. The area and power consumption are found to be 244.46 nm2and 0.31 mW, respectively. AAD achieves 98% accuracy with lower computational and hardware costs compared to mixed pooling, making it an ideal pooling mechanism for an IoT CNN accelerator.

Any sequential learning task relies on the idea of connecting previous time-stamp information to the immediate present time-stamp task to predict the future. The underlying challenge is to understand the hidden patterns in the sequence by means of analyzing short- and long-term dependencies and temporal differences. Recurrent Neural Networks (RNNs) and their variants, such as Long Short-Term Memory (LSTM) are widely used in problem domains like speech recognition, Natural Language Processing (NLP), fault prediction, and language translation modeling over the past few years. Higher accuracy demands complex LSTM network models which lead to high computational cost, area overhead, and excessive power consumption. Reversible logic circuit synthesis, in the context of ideally Zero heat dissipation, has emerged as a new research paradigm for low power circuit designs. In this paper, we have proposed a novel design of LSTM architecture using reversible logic gates. To the best of our knowledge, the proposed approach is the first attempt to implement a complete feedforward LSTM circuit using only reversible logic gates. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA. The comparative analysis demonstrates that the proposed approach has achieved an approximately 17% reduction in overall power dissipation compared to traditional networks. The proposed approach also has better scalability than the classical design approach.

With the advancement of advanced node technology beyond sub-10 nm nodes, high-performance computing is facing a great challenge in the form of excessive levels of heat. Against this limitation, we can re-synthesis any complex digital circuits using reversible logic only, known for ideally Zero-heat dissipation. This paper proposes a novel reversible logic based on Configurable Fault-Tolerant Embryonic Hardware. We have reinvestigated the concept of Self-healing for hardware systems in the context of reversible logic and circuits. This paper presents a comparative analysis between conventional and proposed quantum approach on various parameters such as area-overhead, power dissipation and quantum cost along with the limitations of conventional computing. The reliability of the proposed approach is analyzed against other existing classical approaches with different failure rates. The overall power dissipation is almost 19% lower for the proposed approach compared to other conventional approaches using digital gates with cell number 32. The proposed approach is implemented for the ALU array using VHDL on Altera 10 GX FPGA.

Resources discovery is a fundamental requirement to the full realization of the vision of Internet of Things. Discovery includes resource properties, capabilities, and metadata. It enables consumers to build IoT applications and services that utilize “smart things” with no prior knowledge about these things. This paper studies three of the most commonly used discovery protocols, CoAP, MQTT and UPnP. We compare between their performance and behavior in IoT deployments. Each protocol is implemented and deployed on a mobile phone as a client and a Raspberry Pi as a broker/server. The implementation includes a WeMo switch and a TI SensorTag as resources. The paper provides insights on the different features, behavioural attributes, and a comparative analysis between these protocols. We also present performance indexes of each protocol in terms of memory and CPU usage, latency, and traffic exchange between a publisher and a subscriber. Our analysis shows that despite the three protocols are fundamentally different and each one has pros and cons, they are all highly useful in IoT environments. However, CoAP is generally more flexible and scalable, but requires a higher memory footprint.

Object detection is a fundamental process in traffic management systems and self-driving cars. Deformable part model (DPM) is a popular and competitive detector for its high precision. This paper presents a programmable, low power hardware implementation of DPM based object detection for real-time applications. Our approach employs a very fast object detection pipeline with complementary techniques such as fast feature pyramid, Fast Fourier Transform (FFT) and early classification to accelerate DPM with a reasonable accuracy loss and achieves a speed-up of 50x and 6x over original DPM and cascade DPM respectively on single core CPU. The hardware circuit uses 65nm CMOS technology and consumes only 36.5mW (0.81 nJ/pixel) based on the post-layout simulation. The ASIC has an area of 3362 kgates and 295.5 KB on-chip memory and the design utilizes two simultaneous engines to process two independent object categories with 8 deformable parts per category.

In this paper, self-healing concept for hardware systems is investigated and a new approach is proposed. Hardware systems have been proposing imitations to biological organisms in the way they offer healing and recovery abilities. Digital systems with inspired homogeneous architecture have improved capabilities to compensate for any faults. Self-healing is defined by the ability of a system to detect faults or failures and fix them. One of the main problems in current self-healing approaches is area overhead and scalability for complex structures considering they are based on redundancy and spare blocks. This paper proposes a different approach for self-healing based on embryonic structures without a need for spare cells. The area overhead is lower compared to other approaches relying on spare cells. The proposed approach relies on time multiplexing two functions in one cell within one clock cycle. The reliability of the proposed technique is studied and compared to conventional system with different failure rates. This approach is capable of healing up to 50% of the cells where each cell can cover another neighbor failed cell at most. The area overhead is 9% for the proposed approach which is much lower compared to other approaches using spare cell. The proposed approach is applied to investigate two case studies; ALU array, and neural network.

The Internet of Things (IoT) is a network of Internet‐enabled devices that can sense, communicate, and react to changes in their environment. Billions of these computing devices are connected to the Internet to exchange data between themselves and/or their infrastructure. IoT promises to enable a plethora of smart services in almost every aspect of our daily interactions and improve the overall quality of life. However, with the increasing wide adoption of IoT, come significant privacy concerns to lose control of how our data is collected and shared with others. As such, privacy is a core requirement in any IoT ecosystem and is a major concern that inhibits its widespread user adoption. The ultimate source of user discomfort is the lack of control over personal raw data that is directly streamed from sensors to the outside world. In this survey, we review existing research and proposed solutions to rising privacy concerns from a multipoint of view to identify the risks and mitigations. First, we provide an evaluation of privacy issues and concerns in IoT systems due to resource constraints. Second, we describe the proposed IoT solutions that embrace a variety of privacy concerns such as identification, tracking, monitoring, and profiling. Lastly, we discuss the mechanisms and architectures for protecting IoT data in case of mobility at the device layer, infrastructure/platform layer, and application layer.