This paper presents a high-throughput impedance readout IC with a novel synchronous cyclic integration technique using a scalable capacitive transimpedance stage. The proposed technique removes the need for the low pass filter (LPF) in the readout chain and performs the I/Q demodulation within a single cycle. Fabricated in a 180-nm CMOS process, the proposed IC consumes 50 μW from a 1.2-V supply. It can measure impedances over a frequency of 100 Hz to 100 kHz with an accuracy of 99.7% and can achieve a throughput of 50 kSps at 100 kHz input frequency.

In this paper, a fully-integrated digital low dropout (DLDO) regulator is proposed utilizing a multi-bits shift handler (MBSH), decremental-gain PMOS array, and adaptive coarse loop controller to achieve fast load transient responses with improved line and load regulations. An undershoot-limiter loop (ULL) is also proposed to help to reduce the voltage undershoot peak during load current transients. To significantly mitigate the steady-state voltage ripples (VRIPP) and quiescent current (IQ), we propose a synchronized fine-loop freezer (FLF) in the fine loop of the DLDO that is only activated when VREGgets equal to VREF. The proposed DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.22 mm2. The simulation results demonstrate that the proposed DLDO achieves ≤ 130 μV of VRIPPwhile maintaining a minimum dropout voltage of 20 mV and a peak current efficiency of 99.96 %.

This paper presents a novel high-throughput impedance measurement integrated circuit (IC) with baseline cancellation for neural EIT applications. The proposed technique uses a peak detector to obtain impedance magnitude every cycle. After taking the peak, the peak detector is reset to a DC baseline voltage. And, the signal swinging between the amplitude and the reset baseline is further amplified, allowing to measure small impedance variations even with a large baseline. The proposed IC fabricated in a 180-nm standard CMOS process can measure impedance variations of >0.1% baseline can be measured, while achieving high throughput of 100 kS/s at 100 kHz input frequency. Scalable design allows the proposed IC to support a wide frequency range from 100 Hz to 100 kHz with a power consumption from 31 μW to 39 μW from a 1.2-V supply.

This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (VRIPP) ofRIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (ILOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm2. The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum ILOADof 75 mA with a peak current efficiency of 99.93 %.

This paper presents a wireless, low power and low cost wearable for real time monitoring and analysis of bowling action in the game of cricket. Utilizing flex sensor as an enabling component, the device performs continuous measurement of arm angle within one degree accuracy. The wearable also utilizes a force sensor enabling it to detect the time instant at which the ball is released. The device wirelessly communicates to a smart phone using BLE 4.0, where a complete visual and graphical analysis is performed on the received data, and decision about the legality of action is displayed.