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Kenneth D. Field

dblp:141/7080 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Speech recognition and synthesis · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Natural language and speech › Speech recognition and synthesis
speech coding		 0.011982
Real-Time Speech Coder Implementation on an Array Processor · IEEE Trans. Commun. 1982
Parallel and multicore computing
array processor		 0.011982
Real-Time Speech Coder Implementation on an Array Processor · IEEE Trans. Commun. 1982

Methods — techniques the papers use, named apart from their topics

linear predictive coding · 0.0adaptive predictive coding · 0.0
YearPublicationVenuePosition
1982 Real-Time Speech Coder Implementation on an Array Processor
abstract
The feasibility of a speech coding algorithm is most effectively indicated by its successful real-time implementation. The implementation effort presents issues distinct from those related to the development of the algorithm. Problems of real-time software design and debugging, system reliability, and implementation correctness must be addressed. In addition, the power of a general purpose array processing computer may be required to accomplish the real-time aspect of the implementation. The unique, often highly parallel, architecture of available array processors can present the additional issues of multiprocessor intercommunication and control. This paper considers successful approaches to these issues in the context of two real-time speech coder algorithms implemented on an array processor, a linear predictive baseband coder operating at 9.6 kbits/s, and an adaptive predictive coder operating at 16 kbits/s.
Jared J. Wolf, Kenneth D. Field
 IEEE Trans. Commun.2
1981 Real-time speech coder implementation at 9.6 and 16 kb/s
abstract
The practical feasibility of a speech coding algorithm is most effectively indicated by its successful real-time implementation. The implementation effort presents issues distinct from those related to the development of the algorithm. Problems of real-time software design and debugging, system reliability, and implementation correctness must be addressed. In addition, the power of a special purpose array processing computer is generally required to accomplish the real-time aspect of the implementation. The unique, often highly parallel architecture of available array processors can present the additional issues of multi-processor intercommunication and control. This paper considers successful approaches to these issues in the context of two real-time speech coder algorithms implemented on an array processor (a linear predictive baseband coder operating at 9.6 kb/s, and an adaptive predictive coder operating at 16 kb/s).
Jared J. Wolf, Kenneth D. Field
 ICASSP2