Sequential recommendation is essential in modern recommender systems, focusing on effectively extracting and expressing user representations. Most existing methods rely on deep neural networks that employ a single vector for user interests, neglecting their multi-dimensional nature. This limitation hampers the accurate representation of user preferences. Meanwhile, with the development of deep learning and large models, the growing complexity of deep learning models increases hardware and training costs. In this paper, SCAD (Advancing Sequence Augmentation with Coupling Attention Dynamic Routing), a neighbor-based sequential recommender model, is proposed to tackle these challenges, and it can be regarded as a lightweight recommender system model. SCAD features three main components: the Neighbor Interest Activation (NIA) module, which enhances user representation by exploring similar users; the Coupling Attention Dynamic Routing (CAD) module, which uses a Capsule Network to determine the optimal representation strategy; and the “Interest Merge” module, which integrates single- and multi-interest information for improved preference extraction. Generally speaking, SCAD is superior to most existing methods in constructing user interests, and significantly improves the accuracy of recommendation. Extensive experiments on two real-world benchmarks demonstrate that SCAD outperforms existing top-performance methods in terms of recommendation accuracy.

3D Gaussian Splatting has emerged as a prominent technique for representing and rendering complex 3D scenes, offering high fidelity and speed but resulting in large file sizes. Existing compression methods can reduce 3D Gaussian data size but often require costly retraining or refinement, which is memory- and compute-intensive and lacks flexibility for varying compression needs. This challenge grows as large-scale scenes become more common, increasing the demand for efficient, low-overhead compression methods - especially for resource-constrained mobile and edge devices.

The globalization process for integrated circuits (ICs) raises serious concerns regarding hardware Trojans (HTs). Due to the stealth and variety of HTs, detecting them at test time can be very resource intensive. This situation becomes even worse when the device under test (DUT) contains untrusted third-party intellectual property (3PIP) cores. For systems on chip (SoCs) that rely on untrusted 3PIP cores, this article solves the online HT detection and recovery problem from a graph-theoretic perspective. The proposed graph-theoretic models minimize the implementation cost of the system in terms of both the cost of purchasing different IP cores and the area overhead. To further enhance the security of the system, we also propose schemes to locate and replace an HT-infected IP core. The feasibility and efficiency of the proposed techniques are verified by experiments.

Fabrication-less integrated circuit (IC) design houses outsource fabrication to third-party foundries to reduce cost of manufacturing. The outsourcing of IC fabrication, beyond our expectation, raises concerns regarding intellectual property (IP) piracy and theft by rogue elements in the third-party foundries. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft, and piracy. However, prior work on obfuscation for IP protection has primarily applied to the gate level or the layout level. As a result, it can significantly impact the performance of the original design in addition to requiring redesign of standard cells. In this article, we propose a high-level synthesis and analysis (HLSA)-based obfuscation approach for IP protection. The proposed method is based on split manufacturing. Additional dummy units and MUXes can be added to further obfuscate the design. The proposed technique aligns with the standard-cell-based design methodologies and does not significantly impact the performance of the original design. Our experimental results confirm that the proposed approach can provide high levels of IC obfuscation with moderate area cost.

The outsourcing for fabrication introduces security threats, namely hardware Trojans (HTs). Many design-for-trust (DFT) techniques have been proposed to address such threats. However, many HT detection techniques are not effective due to the dependence on golden chips, limitation of useful information available and process variations. In this paper, we data-mine on path delay information and propose a variation-tolerant path delay order encoding technique to detect HTs.

Reversible logic is a building block for adiabatic and quantum computing in addition to other applications. Since common functions are non-reversible, one needs to embed them into proper-size reversible functions by adding ancillary inputs and garbage outputs. We explore the Intellectual Property (IP) piracy of reversible circuits. The number of embeddings of regular functions in a reversible function and the percent of leaked ancillary inputs measure the difficulty of recovering the embedded function. To illustrate the key concepts, we study reversible logic circuits designed using reversible logic synthesis tools based on Binary Decision Diagrams and Quantum Multi-valued Decision Diagrams.

Many fabrication-less design houses are outsourcing their designs to third-party foundries for fabrication to lower cost. This IC development process, however, raises serious security concerns on Hardware Trojans (HTs). Many design-for-trust techniques have been proposed to detect HTs through observing erroneous output or abnormal side-channel characteristics. Side-channel characteristics such as path delay have been widely used for HT detection and functionality verification, as the changes of the characteristics of the host circuit incurred by the inserted HT can be identified through proper methods. In this article, for the first time, we propose a two-phase technique, which uses the order of the path delay in path pairs to detect HTs. In the design phase, a full-cover path set that covers all the nets of the design is generated; meanwhile, in the set, the relative order of paths in path pairs is determined according to their delay. The order of the paths in path pairs serves as the fingerprint of the design. In the test phase, the actual delay of the paths in the full-cover set is extracted from the fabricated circuits, and the order of paths in path pairs is compared with the fingerprint generated in the design phase. A mismatch between them indicates the existence of HTs. Both process variations and measurement noise are taken into consideration. The efficiency and accuracy of the proposed technique are confirmed by a series of experiments, including the examination of both violated path pairs incurred by HTs and their false alarm rate.

Due to the globalization trend of IC industry, more and more chips are designed and/or fabricated by foreign companies and foundries. Among all the consequences of this globalization trend, the possible existence of stealthy-inserted hardware Trojans (HTs) has raised a great security concern. Without the awareness of the end users or the original designers of host circuits, HTs are usually inserted stealthily at one of the outsourced design or fabrication stages, remain (almost) harmless to the host on dormant mode, and upon triggered will disturb the functions and/or leak the secrets carried by the host. It could become a serious security leak of the systems built on top of infected chips. Identifying whether a circuit carries an HT is thus of the utmost importance to mission-critical applications. Speaking from the point of HT designers, nets with extreme state probabilities could be used to create rare state combination for the purpose of HT triggering. Besides, HT designers seek nets with low switching probabilities to insert their HTs in order not to increase power leakage. We denote the nets with extreme state probability as extreme nets and the nets with low switching probability as inactive nets. It is commonly believed that in order to minimize the chance of accidental triggering or power analysis, they would be better to choose, among all the nets of the host, the nets that with extreme state probabilities (extreme nets) or the nets that barely switch (inactive nets) to construct the trigger parts of their HTs, respectively. However, a net of a circuit experiences very different state probabilities and switching probabilities on test mode and function mode, and existing works have only considered the former. The nets with low activeness on both test mode and function mode hence will be the “best candidates.” In this paper we will first build the ground on finding the nets with low activeness on function mode, and then propose a fast heuristic method approach. The method runs in minimal complexity, has high accuracy, and is tested on popular benchmarks and large-sized circuits.

Tasks in hard real-time systems are required to meet deadlines in the presence of faults. We conclude that a sufficient condition of a task set experiencing its worst-case finish time (WCFT) is that its critical task (CT) incurs all faults. An algorithm is presented to identify the CT and the WCFT in O(N2) with N being the task number. A common practice that bet the WCFT using the task with the longest re-execution time could under estimate by up-to 35%!

Current Integrated Circuit (IC) development process raises security concerns about hardware Trojan which are maliciously inserted to alter functional behavior or leak sensitive information. Most of the hardware Trojan detection techniques rely on a golden (trusted) IC against which to compare a suspected one. Hence they cannot be applied to designs using third party Intellectual Property (IP) cores where golden IP is unavailable. Moreover, due to the stealthy nature of hardware Trojan, there is no technique that can guarantee Trojan-free after manufacturing test. As a result, Trojan detection and recovery at run time acting as the last line of defense is necessary especially for mission-critical applications. In this paper, we propose design rules to assist run-time Trojan detection and fast recovery by exploring diversity of untrusted third party IP cores. With these design rules, we show the optimization approach to minimize the cost of implementation in terms of the number of different IP cores used by the implementation.