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Toshiki Iwata

dblp:142/0570 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Processor architecture and microarchitecture · 50%
Artificial intelligence
1 paper
Speech recognition and synthesis · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
multiprocessor architecture		 0.011985
A Microprocessor for Speech Recognition · IEEE J. Sel. Areas Commun. 1985
Hardware accelerators and domain-specific architectures › signal processing accelerator
speech recognition accelerator		 0.011985
A Microprocessor for Speech Recognition · IEEE J. Sel. Areas Commun. 1985
Natural language and speech › Speech recognition and synthesis › automatic speech recognition
isolated word recognition		 0.011985
A Microprocessor for Speech Recognition · IEEE J. Sel. Areas Commun. 1985

Methods — techniques the papers use, named apart from their topics

pipelined architecture · 0.0dynamic RAM design · 0.0
YearPublicationVenuePosition
1985 A Microprocessor for Speech Recognition
abstract
A new single-chip microprocessor for speech recognition, the SRP, has been developed, utilizing a multiprocessor architecture and a pipelined structure. It can recognize up to 340 isolated words or 40 connected words in real time. The SRP contains a vector distance calculator, a DP-equation calculator, and an I/O controller operating in a pipelined manner. Algorithm variations and operation parameters are user programmable, and the total size of the SRP program for a typical speech recognition system is about 700 words. The device has been fabricated with n-channel Si-gate E/D MOS technology with 2.5 μm design rules and employs 7296 three-transistor dynamic RAM cells for a total of more than 40 000 transistors.
Yuichi Kawakami, Hisao Ishizuka, Masao Watari, Hiroaki Sakoe, Toshiaki Hoshi, Toshiki Iwata
 IEEE J. Sel. Areas Commun.6
1983 A microprocessor for speech recognition
abstract
A new single-chip microprocessor for speech recognition has been developed utilizing multi-processor architecture and pipelined structure. By DP-matching algorithm, the processor recognizes up to 340 isolated words or 40 connected words in realtime.
Hisao Ishizuka, Masao Watari, Hiroaki Sakoe, Seibi Chiba, Toshiki Iwata, Tomoko Matsuki, Yuichi Kawakami
 ICASSP5