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Masao Watari

dblp:142/0709 · DBLP profile ↗
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5ranked-venue papers
2as first author
0since 2021 · last 1986
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 4 · 2 first-authorComputer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Processor architecture and microarchitecture · 50%
Artificial intelligence
1 paper
Speech recognition and synthesis · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
multiprocessor architecture
0.011985
A Microprocessor for Speech Recognition · IEEE J. Sel. Areas Commun. 1985
Hardware accelerators and domain-specific architectures › signal processing accelerator
speech recognition accelerator
0.011985
A Microprocessor for Speech Recognition · IEEE J. Sel. Areas Commun. 1985
Natural language and speech › Speech recognition and synthesis › automatic speech recognition
isolated word recognition
0.011985
A Microprocessor for Speech Recognition · IEEE J. Sel. Areas Commun. 1985

Methods — techniques the papers use, named apart from their topics

pipelined architecture · 0.0dynamic RAM design · 0.0
YearPublicationVenuePosition
1986 Connected digit speech recognition by using demi-word pair reference pattern (DWPR)
abstract
This paper proposes two methods that cope with difficulties in connected digit recognition. One is the 'Demi-Word Pair Reference Pattern(DWPR) Method', which is useful for dealing with the coarticulation effect appearing at the word boundaries. The other is the 'Typically Distorted Pattern (TDP) Method'. This helps prepare robust reference templates including several types of distortion which often occur in natural speech. An experiment has been performed for 20 untrained speakers in speaker-dependent mode. The TDP was gathered from multiple speakers' pattern. The results showed that the TDP+DWPR integrated method achieved considerably higher recognition accuracy (99.0%) than a conventional word-based DP-matching method (97.5%).
Hiromi Fujii, Masao Watari, Hiroaki Sakoe, Seibi Chiba
ICASSP2
1986 New DP matching algorithms for connected word recognition
abstract
In this paper, two new algorithms are proposed to overcome demerits in previous algorithms, such as the CWDP algorithm or the One-Pass algorithm. In the first one, called 'Blockwise DP matching (BWDP) algorithm', the calculation is carried out in step with the block having BL input pattern frames, instead of one frame used in the CWDP algorithm. This reduces the number of memory access times to 1/BL. However, it cannot handle the finite state automaton control with loop transition rules. In the other algorithm, called 'Slant-blockwise DP matching (SBDP) algorithm', the calculation block is inclined to the reference pattern time axis. Calculation is carried out in each slant block with BL frame width. This makes it possible to handle the finite state automaton control with loop transition rules. However, the program for this algorithm is rather complex. Further, improvement concerning variable block width is proposed. It can extend the effective block width. Namely, it can further reduce the number of memory access times.
Masao Watari
ICASSP1
1985 A Microprocessor for Speech Recognition
abstract
A new single-chip microprocessor for speech recognition, the SRP, has been developed, utilizing a multiprocessor architecture and a pipelined structure. It can recognize up to 340 isolated words or 40 connected words in real time. The SRP contains a vector distance calculator, a DP-equation calculator, and an I/O controller operating in a pipelined manner. Algorithm variations and operation parameters are user programmable, and the total size of the SRP program for a typical speech recognition system is about 700 words. The device has been fabricated with n-channel Si-gate E/D MOS technology with 2.5 μm design rules and employs 7296 three-transistor dynamic RAM cells for a total of more than 40 000 transistors.
Yuichi Kawakami, Hisao Ishizuka, Masao Watari, Hiroaki Sakoe, Toshiaki Hoshi, Toshiki Iwata
IEEE J. Sel. Areas Commun.3
1983 A microprocessor for speech recognition
abstract
A new single-chip microprocessor for speech recognition has been developed utilizing multi-processor architecture and pipelined structure. By DP-matching algorithm, the processor recognizes up to 340 isolated words or 40 connected words in realtime.
Hisao Ishizuka, Masao Watari, Hiroaki Sakoe, Seibi Chiba, Toshiki Iwata, Tomoko Matsuki, Yuichi Kawakami
ICASSP2
1983 A speaker independent word recognition based on transient matching
abstract
In speaker independent word recognition, time-normalization problem has not been completely solved at present. In the attempt to solve this problem, this paper proposes an algorithm which takes into consideration nearly invariant properties in the time axis of the transient parts of the speech. Using this algorithm, speaker independent recognition becomes possible by performing multi-dimensional analysis of the transient parts of the speech after transient detection. This algorithm has been applied to 12-word recognition and 101-monosyllable recognition, showing correct rates of about 98 % and 82 %, respectively, for non-learning data.
Masao Watari, Makoto Akabane, Yoichiro Sako
ICASSP1