Norio Suzuki

dblp:142/0800 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 2Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Processor architecture and microarchitecture · 23%
Computer graphics and multimedia
1 paper
Image and video processing · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Image and video processing › real-time image processing
real-time video processing
0.011988
A single-board video signal processor module employing newly developed LSI devices · IEEE J. Sel. Areas Commun. 1988
Hardware accelerators and domain-specific architectures › video processing accelerator
video signal processor
0.011988
A single-board video signal processor module employing newly developed LSI devices · IEEE J. Sel. Areas Commun. 1988
Processor architecture and microarchitecture › microprogramming
microprogrammable processor
0.011988
A single-board video signal processor module employing newly developed LSI devices · IEEE J. Sel. Areas Commun. 1988

Methods — techniques the papers use, named apart from their topics

overlap-save · 0.0overlap-add · 0.0
YearPublicationVenuePosition
1993 Adaptive DPCM for broadcast-quality TV transmission of composite NTSC signal
abstract
This paper proposes a DPCM algorithm to be deployed for broadcast quality transmission of composite NTSC color TV signal at DS-3 rate (45 Mb/s). Recently, many algorithms have been proposed for TV coding and most of them are based on orthogonal transform such as DCT. DCT is appropriate for high compression. On the other hand, DPCM is the best candidate for highest quality transmission, though it might need a comparatively high transmission rate. DPCM can be directly applied to composite NTSC signal without separation/synthesis of chrominance and luminance components before/after the compression. In case of cascaded connection, no accumulation of coding noise can be achieved unlike transform coding. It has been confirmed, using a complete codec running at DS-3 rate, that the proposed adaptive DPCM is very effective even for composite NTSC signals including the CCIR standard sequences. This adaptive DPCM contributes to rapid progress of a digital broadcast TV transmission network using a high speed medium such as SONET as well as DS- 3 service.
Toru Shibuya, Norio Suzuki, Noboru Kawayachi, Toshio Koga
VCIP2
1988 A single-board video signal processor module employing newly developed LSI devices
abstract
A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel*128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system.>
Hidenobu Harasaki, Ichiro Tamitani, Yukio Endo, Takao Nishitani, Masakatsu Yamashina, Tadayoshi Enomoto, Norio Suzuki
IEEE J. Sel. Areas Commun.7
1987 Realtime video signal processor module
abstract
Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a flexible pipelined architecture optimized for L1 or L2-norm distance calculation, used in a wide variety of image processing. The AGU chip, including 15-word register file for pointer alteration, offers a user-friendly two dimensional pointer addressing. A realtime Video Signal Processor Module (VSPM), composed of one PAU, four AGUs and memories, has been implemented for multiprocessor VSP configuration. Thanks to software control capability, various kinds of picture coding techniques can be evaluated by the system.
Hidenobu Harasaki, Ichiro Tamitani, Yukio Endo, Takao Nishitani, Masakatsu Yamashina, Tadayoshi Enomoto, Norio Suzuki
ICASSP7