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Douglas M. Brinthaupt

dblp:142/0853 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › microprocessor design
bit-slice architecture		 0.011988
A bit-slice architecture for sigma-delta analog-to-digital converters · IEEE J. Sel. Areas Commun. 1988
Integrated circuit design
digital circuit design		 0.011988
A bit-slice architecture for sigma-delta analog-to-digital converters · IEEE J. Sel. Areas Commun. 1988
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design		 0.011988
A bit-slice architecture for sigma-delta analog-to-digital converters · IEEE J. Sel. Areas Commun. 1988

Methods — techniques the papers use, named apart from their topics

decimation · 0.0IIR filtering · 0.0FIR filtering · 0.0
YearPublicationVenuePosition
1988 A bit-slice architecture for sigma-delta analog-to-digital converters
abstract
The sigma-delta analog-to-digital converters is based on filtering and undersampling by the digital section of the one-bit output stream coming from the modulation. The structure of this section, consisting of a sine cubic FIR filter decimator followed by an IIR decimator section, is discussed. It is shown that from both signal processing and hardware implementation viewpoints it is advantageous to have the decimation factor of the first stage as large as possible. A bit-slice implementation of the decimation stages is given. It can be easily expanded when higher bit resolutions are required.>
Vladimir Friedman, Douglas M. Brinthaupt, De-Ping Chen, Timothy W. Deppa, John P. Elward Jr., Evelyn M. Fields, Hanafy Meleis
 IEEE J. Sel. Areas Commun.2