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N. Janakiraman 0001

dblp:142/1598 · also Janakiraman Nithiyanantham · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2025
0000-0001-6616-5340ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 1 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 70% Integrated circuit design · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › system-level design
system design methodology
0.011986
Design Examples of System Partitioning and Performance Allocation for VLSI Implementation · IEEE J. Sel. Areas Commun. 1986
Electronic design automation › system-level design
system partitioning
0.011986
Design Examples of System Partitioning and Performance Allocation for VLSI Implementation · IEEE J. Sel. Areas Commun. 1986
Integrated circuit design
VLSI design
0.011986
Design Examples of System Partitioning and Performance Allocation for VLSI Implementation · IEEE J. Sel. Areas Commun. 1986
Electronic design automation
design methodology
0.011986
Design Examples of System Partitioning and Performance Allocation for VLSI Implementation · IEEE J. Sel. Areas Commun. 1986

Methods — techniques the papers use, named apart from their topics

system decomposition · 0.0performance specification · 0.0
YearPublicationVenuePosition
2025 Robust multi-stage deep learning approach for facial recognition and classification
Chirag Chandrashekar, Maheswari Subburaj, Arun Kumar Sivaraman, Ummity Srinivasa Rao, N. Janakiraman 0001, Ajmery Sultana
Neural Comput. Appl.5
2022 A new routing protocol for WSN using limit-based Jaya sail fish optimization-based multi-objective LEACH protocol: an energy-efficient clustering strategy
M. K. Nagarajan, N. Janakiraman 0001, C. Balasubramanian
Wirel. Networks2
1986 Design Examples of System Partitioning and Performance Allocation for VLSI Implementation
abstract
Generally, in the telecommunication industry, VLSI implementation is viewed as a means to cost reduction and is attempted only after successively decomposing a system into circuits corresponding to individual printed circuit boards (PCB's). This traditional "circuit-design" approach is unable to cope with and to exploit the potential of VLSI capabilities such as chip density and processing power. The availability of unprecedented processing power and the recognition of "effective endproduct cost" as the true measure for VLSI chip fabrication are leading the change over from integrated circuit design to integrated system design. In this paper, this emerging system design methodology for VLSI implementation and its two elements, system partitioning and performance specification allocation, are illustrated by two design examples; one relating to line-circuit design and the other to a packet-switch design.
Bhagwati Prasad Agrawal, N. Janakiraman 0001
IEEE J. Sel. Areas Commun.2