This paper presents a novel graph-based deep learning framework for accurate and efficient voltage state estimation across diverse power distribution networks. The proposed model integrates topology-aware encoding, temporal memory propagation, and uncertainty-aware decoding within a federated learning architecture, enabling scalable deployment under partial observability and communication constraints. Experiments on three benchmark datasets, IEEE 33-Bus, IEEE 123-Bus, and European LV, demonstrate that the proposed method consistently outperforms state-of-the-art baselines. Specifically, it achieves the lowest average RMSE of 0.25, 0.31, and 0.29 across the three systems, representing up to a 32.4% reduction compared to standard GNNs. MAE is similarly improved to 0.18, 0.22, and 0.21, while MAPE is reduced to 1.5%, 2.0%, and 1.7%. Beyond accuracy, the model demonstrates superior efficiency, requiring only 87 M FLOPs and 448 MB of peak VRAM, and converging 30% faster than comparable baselines. Ablation studies confirm the essential role of each architectural component, and uncertainty visualization validates the model’s calibrated confidence across time and topology. The proposed approach balances predictive performance, computational tractability, and robustness, providing a promising solution for next-generation intelligent grid state monitoring under real-world constraints such as sensor sparsity, data heterogeneity, and edge deployment limitations.

Deep learning has significantly advanced Electronic Design Automation (EDA), with circuit representation learning emerging as a key area for modeling the relationship between a circuit’s structure and functionality. Existing methods primarily use either Large Language Models (LLMs) for Register Transfer Level (RTL) code analysis or Graph Neural Networks (GNNs) for netlist modeling. While LLMs excel at high-level functional understanding, they struggle with detailed netlist behavior. GNNs, however, face challenges when scaling to larger sequential circuits due to long-range information dependencies and insufficient functional supervision, leading to decreased accuracy and limited generalization. To address these challenges, we propose MOSS, a multimodal framework that integrates GNNs with LLMs for sequential circuit modeling. By enhancing D-type Flip-Flop (DFF) node features with embeddings from fine-tuned LLMs on RTL code, we focus the GNN on critical anchor points, reducing reliance on long-range dependencies. The LLM also provides global circuit embeddings, offering efficient supervision for functionality-related tasks. Additionally, MOSS introduces an adaptive aggregation method and a two-phase propagation mechanism in the GNN to better model signal propagation and sequential feedback within the circuit. Experimental results demonstrate that MOSS significantly improves the accuracy of functionality and performance predictions for sequential circuits compared to existing methods, particularly in larger circuits where previous models struggle. Specifically, MOSS achieves a $\mathbf{9 5. 2 \%}$ accuracy in arrival time prediction.

As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric for functional safety is achieving a sufficient fault coverage. To meet this requirement, extensive time-consuming fault simulation of the RTL code is necessary during the chip design phase. The main overhead in RTL fault simulation comes from simulating behavioral nodes (always blocks). Due to the limited fault propagation capacity, fault simulation results often match the good simulation results for many behavioral nodes. A key strategy for accelerating RTL fault simulation is the identification and elimination of redundant simulations. Existing methods detect redundant executions by examining whether the fault inputs to each RTL node are consistent with the good inputs. However, we observe that this input comparison mechanism overlooks a significant amount of implicit redundant execution: although the fault inputs differ from the good inputs, the node's execution results remain unchanged. Our experiments reveal that this overlooked redundant execution constitutes nearly half of the total execution overhead of behavioral nodes, becoming a significant bottleneck in current RTL fault simulation. The underlying reason for this overlooked redundancy is that, in these cases, the true execution paths within the behavioral nodes are not affected by the changes in input values. In this work, we propose a behavior-level redundancy detection algorithm that focuses on the true execution paths. Building on the elimination of redundant executions, we further developed an efficient RTL fault simulation framework, Eraser. Experimental results show that compared to commercial tools, under the same fault coverage, our framework achieves a 3.9 × improvement in simulation performance on average.

With the rapid development of safety-critical applications such as autonomous driving and embodied intelligence, the functional safety of the corresponding electronic chips becomes more critical. Ensuring chip functional safety requires performing a large number of time-consuming RTL fault simulations during the design phase, significantly increasing the verification cycle. To meet time-to-market demands while ensuring thorough chip verification, parallel acceleration of RTL fault simulation is necessary. Due to the dynamic nature of fault propagation paths and varying fault propagation capabilities, task loads in RTL fault simulation are highly imbalanced, making traditional single-dimension parallel methods, such as structural-level parallelism, ineffective. Through an analysis of fault propagation paths and task loads, we identify two types of tasks in RTL fault simulation: tasks that are few in number but high in load, and tasks that are numerous but low in load. Based on this insight, we propose a two-dimensional parallel approach that combines structural-level and fault-level parallelism to minimize bubbles in RTL fault simulation. Structural-level parallelism combining with work-stealing mechanism is used to handle the numerous low-load tasks, while fault-level parallelism is applied to split the high-load tasks. Besides, we deviate from the traditional serial execution model of computation and global synchronization in RTL simulation by proposing a unified computation/global synchronization scheduling approach, which further eliminates bubbles. Finally, we implemented a parallel RTL fault simulation framework, RIROS. Experimental results show a performance improvement of 7.0× and 11.0× compared to the state-of-the-art RTL fault simulation and a commercial tool.

Digital twin technology is transforming the way power grid infrastructure is monitored and managed, yet accurate pattern recognition under complex visual conditions remains a significant challenge. Traditional edge- or feature-based methods struggle to maintain robustness in environments affected by fog, shadow, or occlusion. This paper proposes a fusion framework that combines multi-scale edge detection and SIFT-based local descriptors, integrated through a learnable attention mechanism that adaptively weights features at each pixel location. The method is evaluated on a custom UAV-acquired dataset containing high-resolution power grid imagery under diverse environmental scenarios. Experimental results demonstrate that the proposed approach significantly outperforms edge-only, SIFT-only, and U-Net models across SSIM, F1-score, and IoU metrics, while maintaining practical inference speed. The model also achieves the lowest 3D registration error in point cloud alignment. These results confirm the effectiveness of our method and highlight its potential for accurate, robust digital twin construction in real-world grid inspection systems.