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Jean-Marie Bussat

dblp:142/3925 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 44% Hardware accelerators and domain-specific architectures · 44% Interconnection networks and networks-on-chip · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › scientific computing accelerator
brain simulation accelerator
0.212014
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations · Proc. IEEE 2014
Emerging computing paradigms
neuromorphic computing
0.212014
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations · Proc. IEEE 2014
Interconnection networks and networks-on-chip › network topology
tree networks
0.112014
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations · Proc. IEEE 2014

Methods — techniques the papers use, named apart from their topics

tree network interconnection · 0.2shared electronic circuits · 0.2analog circuit design · 0.2
YearPublicationVenuePosition
2014 Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations
abstract
In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements-axonal arbor, synapse, dendritic tree, and soma-with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time-for the first time-using 16 Neurocores integrated on a board that consumes three watts.
Ben Varkey Benjamin, Peiran Gao, Emmett McQuinn, Swadesh Choudhary, Anand Chandrasekaran, Jean-Marie Bussat, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Kwabena Boahen 0001
Proc. IEEE6