Roy Spliet

dblp:142/4520 · DBLP profile ↗
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2ranked-venue papers
2as first author
1since 2021 · last 2022
0000-0003-2373-1087ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Embedded and real-time systems · 42% Hardware accelerators and domain-specific architectures · 38% Processor architecture and microarchitecture · 19%
Software engineering, system software, and programming languages
1 paper
Operating systems · 50% Concurrent programming · 50%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
data-parallel accelerator
0.612022
Sim-D: A SIMD Accelerator for Hard Real-Time Systems · IEEE Trans. Computers 2022
Embedded and real-time systems › real-time embedded systems
hard real-time systems
0.612022
Sim-D: A SIMD Accelerator for Hard Real-Time Systems · IEEE Trans. Computers 2022
Processor architecture and microarchitecture
SIMD
0.612022
Sim-D: A SIMD Accelerator for Hard Real-Time Systems · IEEE Trans. Computers 2022
Hardware accelerators and domain-specific architectures › data-parallel accelerator
SIMD accelerator
0.612022
Sim-D: A SIMD Accelerator for Hard Real-Time Systems · IEEE Trans. Computers 2022
Embedded and real-time systems
worst-case execution time analysis
0.612022
Sim-D: A SIMD Accelerator for Hard Real-Time Systems · IEEE Trans. Computers 2022
Operating systems › real-time systems
real-time operating systems
0.212014
Fast on Average, Predictable in the Worst Case: Exploring Real-Time Futexes in LITMUSRT · RTSS 2014
Concurrent programming
synchronization
0.212014
Fast on Average, Predictable in the Worst Case: Exploring Real-Time Futexes in LITMUSRT · RTSS 2014
Embedded and real-time systems
real-time scheduling
0.112014
Fast on Average, Predictable in the Worst Case: Exploring Real-Time Futexes in LITMUSRT · RTSS 2014
Embedded and real-time systems › real-time scheduling
worst-case analysis
0.112014
Fast on Average, Predictable in the Worst Case: Exploring Real-Time Futexes in LITMUSRT · RTSS 2014

Methods — techniques the papers use, named apart from their topics

cycle-accurate timing model · 0.6priority inheritance protocol · 0.4multiprocessor priority ceiling protocol · 0.4futex · 0.4flexible multiprocessor locking protocol · 0.4
YearPublicationVenuePosition
2022 Sim-D: A SIMD Accelerator for Hard Real-Time Systems
abstract
Emerging safety-critical systems require high-performance data-parallel architectures and, problematically, ones that can guarantee tight and safe worst-case execution times. Given the complexity of existing architectures like GPUs, it is unlikely that sufficiently accurate models and algorithms for timing analysis will emerge in the foreseeable future. This motivates our work on Sim-D, a clean-slate approach to designing a real-time data-parallel architecture. Sim-D enforces a predictable execution model by isolating compute- and access resources in hardware. The DRAM controller uninterruptedly transfers tiles of data, requested by entire work-groups. This permits work-groups to be executed as a sequence of deterministic access- and compute phases, scheduling phases from up to two work-groups in parallel. Evaluation using a cycle-accurate timing model shows that Sim-D can achieve performance on par with an embedded-grade NVIDIA TK1 GPU under two conditions: applications refrain from using indirect DRAM transfers into large buffers, and Sim-D's scratchpads provide sufficient bandwidth. Sim-D's design facilitates derivation of safe WCET bounds that are tight within 12.7 percent on average, at an additional average performance penalty of$\sim$9.2 percent caused by scheduling restrictions on phases.
Roy Spliet, Robert Mullins 0001
IEEE Trans. Computers1
2014 Fast on Average, Predictable in the Worst Case: Exploring Real-Time Futexes in LITMUSRT
abstract
This paper explores the problem of how to improve the average-case performance of real-time locking protocols, preferably without significantly deteriorating worst-case performance. Motivated by the futex implementation in Linux, where uncontended lock operations under the Priority Inheritance Protocol (PIP) do not incur mode-switching overheads, we extend this concept to more sophisticated protocols, namely the PCP, the MPCP and the FMLP+. We identify the challenges involved in implementing futexes for these protocols and present the design and evaluation of their implementations in LITMUSRT, a real-time extension of the Linux kernel. Our evaluation shows substantial improvements in the uncontended case (e.g., A futex implementation of the PCP lowers lock acquisition and release overheads by up to 75% and 92%, respectively), at the expense of some increases in worst-case overhead on par with Linux's existing futex implementation.
Roy Spliet, Manohar Vanga, Björn B. Brandenburg, Sven Dziadek
RTSS1