This brief presents a cross-temperature continuous tracking system for minimum voltage point (CTC-MVPT) based on a universal delay chain (UDC) with multiple monitoring points. By leveraging the timing information provided by the timing margin indicator and timing error indicator, the CTC-MVPT system enables continuous cross-temperature tracking of the minimum voltage point (MVP), significantly reducing power. Meanwhile, the two-step adjustment technique greatly shortens the time required for voltage regulation. In addition, this work further optimizes the 0-to-1 and 1-to-0 transition deviations of the UDC. Measurement results in a 22-nm technology show that the proposed CTC-MVPT system achieves up to 17.7% power reduction over the traditional adaptive voltage scaling (AVS) system as the temperature increases from$0~^{\circ }$C to$80~^{\circ }$C. Therefore, it takes only 1.17ms to adjust the voltage from 0.55 to 0.41 V, representing a 47.8% reduction compared to the traditional scheme. Under the TT corner, the maximum deviation rate of the UDC is only 1.5%, and the maximum deviation between 0-to-1 and 1-to-0 transitions is merely 1.2%. Meanwhile, the system achieves a power gain of up to 55.3% with only a 0.26% area overhead for timing monitoring.

Error detection and correction (EDC) techniques are conventionally employed in dynamic voltage and frequency scaling (DVFS) systems to eliminate timing margins preserved in ICs. However, existing error detection methods generate warning signals even when no violations occur, resulting in frequent corrections that degrade system throughput. This issue of inaccurate detection worsens with further scaling. To solve this issue, this paper presents an accuracy-oriented EDC scheme, AO-EDC. An accurate detection method, consisting of a propagation detector (PD) and an improved half-path-point insertion method, is proposed. PDs that filter out signals from other paths are inserted at the half-path points of selected paths, reducing inaccurate detection by up to 77.5%. In addition, a half-cycle clock gating circuit is proposed to reduce the redundancy of corrections. Implemented on a 22-nm process FIR circuit, post-layout simulation results demonstrate a 42.4% - 50.0% power reduction and a 106.7% - 1089.9% frequency gain at 0.9 - 0.55 V. The proposed scheme triggers fewer corrections and reduces correction timing waste, addressing the throughput degradation issue during over-scaling in DVFS systems.

In this brief, a unified voltage frequency regulator (UVFR) system is designed to eliminate the voltage margin induced by process, voltage, and temperature (PVT) variations. The frequency is regulated with voltage by a universal logic line oscillator (ULLO), which can protect the system from timing violations. The length of the ULLO is self-calibrated by a ULL-based time-digital converter (ULL-TDC) and an in situ half-critical path timing detector, where the ULL is designed to track the critical path delay. A fully synthesizable digital low dropout (DLDO) is designed with the ULL-TDC and a proportional differential (PD) circuit for voltage regulation. The proposed system is implemented in an ARM Cortex-M0 microcontroller in 22 nm technology. Simulation results show that the ULL can accurately track the critical path delay with a maximum variation of 3% at 0.6 V and 11.5% at 0.45 V. The UVFR system consumes 13.2–112 uW of power overhead, and eliminates the voltage margin by 22.3%–28% while reducing the power consumption by 35%–42.3%.

In this paper we analyze the problem of waveform design for target detection in the presence of clutter and noise environment. We use the target priori characteristics to design the transmitted waveform. The waveform is designed by mutual information criterion. Firstly, we present the signal model and information theoretic approach to design waveform. Secondly, we discuss the waveform design is the one that maximizing mutual information between the target priori characteristics and the radar received signal. The results of simulation evaluate the efficiency of the proposed method to compare with the chirp signal.