With increased outsourcing of intellectual property (IP) cores to third-party vendors, system-on-chip designs face heightened security risks from hardware trojans (HTs) that can compromise integrity and functionality. Prior HT detection works typically train separate deep-learning models on combinational (TRTC-TC) and sequential (TRTC-TS) trojan benchmarks from the LEDA-based Trust-Hub dataset, treating them independently and framing detection as binary classification, which fails when both trojan types coexist in a single netlist. In contrast, our proposed method employs a unified Graph Neural Network (GNN)-based model trained on a mixed dataset comprising benchmarks from both TRTC-TC and TRTC-TS, enabling multi-class classification to distinguish between benign, combinational, and sequential trojans. The approach addresses key GNN constraints and attains strong detection performance on the mixed dataset: TPR of 99.3% and 100%, TNR of 99.99% and 99.9%, and PPV of 97.9% and 97% for combinational and sequential trojans, respectively.

Silicon physical unclonable function (PUF) has emerged as a promising spoof-proof solution for low-cost device authentication. Due to practical constraints in preventing phishing through a public network or insecure communication channels, simple PUF-based authentication protocol with unrestricted queries and transparent responses is vulnerable to modeling and replay attacks. In this article, we present a modeling attack resistant PUF-based mutual authentication scheme to mitigate the practical limitations in applications where a resource-rich server authenticates a device with no strong restriction imposed on the type of PUF design or any additional protection on the binary channel used for the authentication. Our scheme uses an active deception protocol to prevent machine learning (ML) attacks on a device with a monolithic integration of a genuine strong PUF (SPUF), a fake PUF, a pseudorandom number generator (PRNG), a register, a binary counter, a comparator, and a simple controller. The hardware encapsulation makes the collection of challenge-response pairs (CRPs) easy for model building during enrollment but prohibitively time consuming upon device deployment through the same interface. A genuine server can perform a mutual authentication with the device using a combined fresh challenge contributed by both the server and the device. The message exchanged in clear cannot be manipulated by the adversary to derive unused authentic CRPs. The adversary will have to either wait for an impractically long time to collect enough real CRPs by directly querying the device or the ML model derived from the collected CRPs will be poisoned. The false PUF multiplexing is fortified against the prediction of waiting time by doubling the time penalty for every unsuccessful guess. Our implementation results on field-programmable gate array (FPGA) device and security analysis have corroborated the low hardware overheads and attack resistance of the proposed deception protocol.

Approximate computing, for error-tolerant applications, provides trade-offs for computations to achieve improved speed and power performance. Approximate circuits, in particular approximate arithmetic circuits, directly affect the performance of a computing system. Hence, approximate circuit designs have been extensively studied. However, security issues of approximate circuits have been ignored. Moreover, hardware Trojans have been found in fabricated chips in manufacturing industry chains by untrusted foundries. Hardware Trojans could affect the functionality of approximate circuits under very rare circumstances with inconsiderable footprints. In this paper, hardware Trojan insertion methods based on signal transition probability are utilized to investigate and evaluate the security threats in approximate circuits. A approximate low-partor-adder (LOA) adder is utilized as an example and analyzed in the paper. The evaluation results show that with the increase of the number of approximation modules, the approximate LOA adder is more possible to be inserted hardware Trojans than the exact LOA adder.

Hardware Trojans (HTs) are acknowledged as a significant emerging security concern in the IC industry resulting from the globalization of the semiconductor supply chain. Recently, taking advantage of the exponential growth in computing power, machine learning (ML) approaches such as neural networks (NNs) are being considered for HT detection. However, the circuit structure and components of an IC design are different from the data types in the ML models. To efficiently extract HT features from complex IC designs and utilize common ML-based detection approaches is challenging. In this paper, a novel HT feature extraction strategy based on gate-level circuit netlists is proposed to tackle the challenges. The HT features are extracted from the circuit topology rather than statistical analysis in previous research. A commonly utilized support vector machine (SVM)-based HT detection model is employed for data training and testing using the extracted features on HT benchmarks from both open-sourced library and HT generation platform to prove the feasibility and efficiency of the proposed HT feature extraction strategy. The detection results show high recall in nearly all tested benchmarks, achieving at most 97.7% recall on sequential Trojans and 84.8% on combinational ones.

Massive Multiple-Input Multiple-Output (MIMO) is an emerging research field due to the increasing demand of spectral efficiency in wireless broadband systems, such as Long Term Evolution (LTE) which is proposed by 3GPP (Third Generation Partnership Project). Precoding is important to exploit the performance of massive MIMO, and codebook design is crucial due to the limited feedback channel. In this paper, we propose a novel double codebook design method based on a Kronecker-type approximation of the array correlation structure for the uniform rectangular array, which is preferable for the antenna deployment of massive MIMO systems. As a case study, we run simulations based on assumptions of the LTE-Advanced system which is extended to 32 dual-polarized antennas. The results verify that the proposed codebook design has remarkable performance gain compared to the traditional double codebook under the uniform rectangular array setup.