Multiprocessor systems-on-chip (MPSoCs) have become the foundation of critical applications in AI, IoT, and autonomous systems. The Network-on-Chip (NoC) is the communication backbone of MPSoCs, enabling smooth and scalable communication between processing elements. Keeping it secure against evolving threats is imperative. Modern processor vulnerabilities expose MPSoCs to threats like timing side-channel (TSC) and denial-of-service (DoS) attacks, where attackers can infect IP blocks at runtime to target the NoC. This is especially concerning in shared-resource environments, where the lack of strict isolation between components enables wider propagation of such attacks. Routing within isolated secure zones can efficiently deal with such attacks. However, existing secure-zone-based approaches are based on routing tables, which become inefficient and unscalable with increases in NoC sizes, necessitating an adaptive and logic-based approach. Although the scalability offered by the latter increases, it is limited in coverage of complex topologies. This paper presents a logic-based distributed routing strategy using the divide-and-conquer principle (LBDRr). It enhances the topological coverage of traditional LBDR methodologies by dividing irregular topologies into a combination of minimal path sub-topologies. (LBDRr) is used to isolate sensitive data within secure zones, ensuring the system’s integrity against interapplication attacks. Experimental results validate the efficacy of the proposed routing algorithm. Its performance was evaluated by comparison with a state-of-the-art routing table-based approach, demonstrating improved performance, security, and scalability.

Trusted Execution Environments (TEEs) enable secure code execution on machines that are not fully trusted by the user who runs the workload. However, existing TEE solutions mostly target CPUs and are typically tied to one specific instruction set architecture. Although some accelerators also provide support for TEEs, this leads to multiple, different TEE implementations on the same system, increasing its complexity and trusted computing base (TCB). This challenge becomes particularly apparent when workloads span heterogeneous processing units, because the diversity of TEE implementations complicates the creation of secure communication channels between the individual TEEs.

The rise of Hardware Trojans (HTs) presents a major threat to the dependability of contemporary electronic systems. Logic testing-based HT detection can identify HTs without a reference-free or golden circuit. In this work, we present a survey of current logic testing-based HT detection that considers Sandia Controllability/ Observability Analysis Program (SCOAP) factors. In order to detect HTs with unique features, the community may use this survey to summarize how SCOAP parameters have been modified over time and are widely utilized as features for machine learning and threshold-based HT detection. We evaluate the state of work to date and outline the main areas for future research in our conclusion.

Nowadays, digital devices like sensors, cell phones, and home servers are deeply embedded in our world to make our daily lives easier. Since we heavily rely on these systems, it is crucial to guarantee their correct functionality and to ensure security and privacy properties. As systems become increasingly complex, it is difficult to maintain security since it necessitates a thorough understanding of all functionalities in hardware and software. Complexity may lead to vulnerabilities that malicious components can exploit. These components can compromise security features provided by the processing cores and the operating system (OS), jeopardizing the overall trustworthiness of the system. In this article, we provide a secure-by-default hardware/OS co-design to build a substrate for trustworthy computing in digital devices. The design is based on a tiled architecture that can integrate untrusted hardware components. Instead of relying on isolation mechanisms of potentially malicious components, isolation is achieved by dedicated and independent hardware components called trusted communication units (TCUs). By keeping the attack surface small and isolating all components by default, malicious hardware and software are restricted in access permissions and, hence, cannot easily break the system’s security. We implemented a TCU-based multiprocessor architecture in a silicon research chip, called Masur23, and ran transfer workloads and selected portions of the microkernel-based OS M3. Our measurements demonstrate the feasibility of such a hardware/OS co-design for trustworthy computing. Compared to the entire chip implementation, security features require minimal latency, area, and power consumption overhead.

Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 x 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 μs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.

Multiprocessor systems-on-chip with distributed memories and task processing are promising architectures to tackle processing demands of edge-cloud applications for autonomous vehicles. We present a novel model which allows estimation of the speedup when memory pooling is combined with prefetching. Processing time and data transfer time are both taken into account. In our scenario, memory pooling enables utilization of remote memories and prefetching hides the additional latency. The model shows speedups of up to 200% for data-intensive processing scenarios. Our approach shows that reasonable performance gains can be achieved when increasing flexibility of the memory architecture.

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

The field of machine-to-machine (M2M) communications has gained wide popularity and is steadily growing. This paper studies the feasibility of using the Global System for Mobile Communications and in particular the General Packet Radio Service (GPRS) for a low data rate long- lasting battery-powered operation of M2M devices. A model is introduced to estimate the power consumption of a GPRS connection. It allows the identification and evaluation of optimizations of the data transmission procedures. Two M2M modes of GPRS operation are introduced. For applications with frequent transmissions, an Always- on-mode turns out to be most reasonable. For infrequent transmissions, e.g., one transmission every 2 hours, an On/off-mode reduces the power consumption of M2M devices by 93% as compared to the Always-on-mode. With a 3-cell battery providing 25.9 Wh of energy and considering only the power consumption of the communication module, a battery lifetime of up to 5 years is feasible. Measurements show that usually 40% of the energy spent for a short data transmission is wasted by one particular GPRS procedure called non-DRX period. Avoiding this saves up to 35% of total average power, depending on the rate of data transmissions.