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Po-Hsun Chang

dblp:143/1269 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 92% Emerging computing paradigms · 8%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.212016
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Electronic design automation › physical design
routing
0.212016
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Electronic design automation › signal integrity
crosstalk
0.112016
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Emerging computing paradigms
noise mitigation
0.112016
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016

Methods — techniques the papers use, named apart from their topics

hierarchical deterministic layout synthesis · 0.2
YearPublicationVenuePosition
2018 A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A
abstract
Decoding high code rate Turbo codes by their reciprocal dual trellis has been shown to be potentially beneficial in implementation due to the simpler trellis structures. However, reciprocal dual trellis decoders' complexity grows significantly when the code rate is less than 1/2. Further, designing a multi-code rate reciprocal dual trellis decoder is even more challenging if periodical puncturing patterns is not always available. In this paper, a radix-4 hybrid-trellis LTE-A turbo decoder with a controller switching between the conventional trellis and the reciprocal dual trellis is presented. To accommodate all the rates defined in LTE-A, a zero patching scheme is proposed to create the periodical puncturing patterns required by the reciprocal dual trellis decoding. The implementation of the proposed decoder supports all the code rates, from 1/3 to 0.95, and all the 188 block lengths. Fabricated in TSMC TN28HPM process, the post-layout simulations show the proposed decoder could achieve 333Mbps at 6 iterations under 263MHz operating frequency. The core area is 1.08 mm2, and the decoder draws 295.57 mW of power with energy efficiency of 0.148(nJ/bit/iter).
Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang
ISCAS1
2016 DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths
abstract
With shrinking process technology, decreasing supply voltage, and increasing clock frequency, noise reduction becomes more and more crucial to the success of modern mixed-signal system-on-chip design. To eliminate the switching noise due to crosstalk coupling between analog and digital signals, it is essential to fully separate the routing paths of analog and digital nets when generating mixed-signal layouts. Different from previous works which cannot fully separate analog and digital routing paths, this paper presents a novel hierarchical deterministic mixed-signal layout synthesis approach with the separation of analog and digital signal paths for switching noise elimination. Experimental results based on a third-order Σ Δ modulator show that the proposed approach can result in various layouts with separated analog and digital signal paths while achieving better signal-to-noise and distortion ratio, and overall performance specifications.
Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2