Demo Data from EDBT 2026 / reviewers in the wild / expert
Young Min Park
dblp:143/3948
· DBLP profile ↗
5ranked-venue papers
1as first author
2since 2021 · last 2023
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Storage systems · 59% Memory systems · 25% Energy-efficient computing · 16% |
Topics — the 13 heaviest of 14, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
flash and SSD |
1.1 | 2 | 2023 | Unified Wear-Leveling Technique for NVM-Based Buffer of SSD · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 Multitoken-Based Power Management for NAND Flash Storage Devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Storage systems
storage reliability |
0.8 | 2 | 2023 | Unified Wear-Leveling Technique for NVM-Based Buffer of SSD · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 Multitoken-Based Power Management for NAND Flash Storage Devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Storage systems › flash and SSD › flash-aware data management
SSD-aware bufferpool management |
0.7 | 1 | 2023 | Unified Wear-Leveling Technique for NVM-Based Buffer of SSD · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Storage systems › flash and SSD › flash memory management
wear leveling |
0.7 | 1 | 2023 | Unified Wear-Leveling Technique for NVM-Based Buffer of SSD · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Storage systems › flash and SSD › flash memory › NAND flash
NAND flash storage |
0.4 | 1 | 2020 | Multitoken-Based Power Management for NAND Flash Storage Devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Energy-efficient computing
power management |
0.4 | 1 | 2020 | Multitoken-Based Power Management for NAND Flash Storage Devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Energy-efficient computing
storage power management |
0.4 | 1 | 2020 | Multitoken-Based Power Management for NAND Flash Storage Devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Memory systems › DRAM › DRAM architecture
3D-stacked DRAM |
0.3 | 1 | 2018 | EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory · IEEE Trans. Computers 2018 |
Memory systems › DRAM
DRAM refresh |
0.3 | 1 | 2018 | EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory · IEEE Trans. Computers 2018 |
Memory systems › virtual memory management
page table management |
0.3 | 1 | 2018 | EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory · IEEE Trans. Computers 2018 |
Memory systems › DRAM › DRAM refresh
refresh energy reduction |
0.3 | 1 | 2018 | EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory · IEEE Trans. Computers 2018 |
Memory systems
non-volatile memory |
0.2 | 1 | 2023 | Unified Wear-Leveling Technique for NVM-Based Buffer of SSD · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Energy-efficient computing › power management
memory power management |
0.1 | 1 | 2018 | EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory · IEEE Trans. Computers 2018 |
Methods — techniques the papers use, named apart from their topics
hot data detection · 0.7token-based power management · 0.4deadlock resolution · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Machine-learning enhancement of urine dipstick tests for chronic kidney disease detectionabstractOBJECTIVE: Screening for chronic kidney disease (CKD) requires an estimated glomerular filtration rate (eGFR, mL/min/1.73 m2) from a blood sample and a proteinuria level from a urinalysis. We developed machine-learning models to detect CKD without blood collection, predicting an eGFR less than 60 (eGFR60 model) or 45 (eGFR45 model) using a urine dipstick test. MATERIALS AND METHODS: The electronic health record data (n = 220 018) obtained from university hospitals were used for XGBoost-derived model construction. The model variables were age, sex, and 10 measurements from the urine dipstick test. The models were validated using health checkup center data (n = 74 380) and nationwide public data (KNHANES data, n = 62 945) for the general population in Korea. RESULTS: The models comprised 7 features, including age, sex, and 5 urine dipstick measurements (protein, blood, glucose, pH, and specific gravity). The internal and external areas under the curve (AUCs) of the eGFR60 model were 0.90 or higher, and a higher AUC for the eGFR45 model was obtained. For the eGFR60 model on KNHANES data, the sensitivity was 0.93 or 0.80, and the specificity was 0.86 or 0.85 in ages less than 65 with proteinuria (nondiabetes or diabetes, respectively). Nonproteinuric CKD could be detected in nondiabetic patients under the age of 65 with a sensitivity of 0.88 and specificity of 0.71. DISCUSSION AND CONCLUSIONS: The model performance differed across subgroups by age, proteinuria, and diabetes. The CKD progression risk can be assessed with the eGFR models using the levels of eGFR decrease and proteinuria. The machine-learning-enhanced urine-dipstick test can become a point-of-care test to promote public health by screening CKD and ranking its risk of progression. Eun Chan Jang, Young Min Park, Hyun Wook Han, Christopher Seungkyu Lee, Eun Seok Kang, Yu Ho Lee, Sang Min Nam |
J. Am. Medical Informatics Assoc. | 2 |
| 2023 | Unified Wear-Leveling Technique for NVM-Based Buffer of SSDabstractSince the gradual emergence of DRAM cost issues from the perspective of solid-state drive (SSD) system design, studies to replace DRAM buffer with a nonvolatile memory (NVM) have been conducted. However, the inferior durability of NVM requires additional wear-leveling algorithms for the buffer. Related works on the wear-leveling of the SSD internal buffer are significant only for specific applications or restricted partitions separated by user data and metadata. This article proposes a novel wear-leveling technique that covers the entire buffer without being constrained by specific applications. We introduce metadata characteristic-aware allocation (MCAA), which utilizes an appropriate hot data detection scheme depending on the type of update pattern on metadata. We also propose unified wear-leveling (UWL) that hierarchically integrates the wear-leveling techniques of each partition, including MCAA. The proposed method improves the maximum write count by 39.3% and the standard deviation of the wear-out by 25.9% on average compared to the conventional technique. Young Min Park, Joonhyeok Yeom, Eui-Young Chung |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2020 | Multitoken-Based Power Management for NAND Flash Storage DevicesabstractNAND flash-based storage devices (NFSDs) have been widely employed in various systems, including cloud servers as well as mobile devices. The core component of NFSDs is NAND flash memory (NFM) which has several advantages over the conventional hard disk drives (HDDs). An NFSD typically adopts a bunch of NFMs which are operated in parallel for maximizing the I/O throughput. However, optimizing for performance may not be desirable from the power budget (PB) perspective. In other words, concurrent operations of NFMs often drain inordinate current, which leads to the violation of the PB allocated for a storage device. In this article, we propose a novel power management scheme which maximizes concurrent operations of NFMs under the given power constraint. The proposed method quantizes the given power constraint of an NFSD. A quantum also called token is the basic unit of power management. The proposed power management scheme allocates tokens to NFMs and only the NFMs having enough tokens can perform their operations. We call this method multitoken-based power management (MTPM). The critical issue of MTPM is a deadlock which is resolved with the key allocation scheme. Furthermore, we enhance MTPM to improve performance. The extended method called keyless MTPM (KMTPM) improves the overall performance by relaxing the key acquisition requirement and allowing subatomic operations. In the experimental results, we confirm that the proposed methods always meet the given power constraint. The proposed KMTPM improves throughput by 22.85% compared to state of the art technique. In addition, KMTPM only incurs 3.8% of performance overhead and 0.015% of area overhead. Tae-Hee You, Sangwoo Han, Young Min Park, Hyuk-Jun Lee, Eui-Young Chung |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2018 | EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM MemoryabstractFor future exascale computing systems, ultra-high-density memories would be required that consume low power to process massive data. Of the various memory devices, 3D-stacked DRAMs using TSVs are a perfect solution for this purposes. In addition to providing high capacity, these provide functional flexibility to the computing system by attaching a logic die in each 3D-stacked DRAM chip. However, the high capacity 3D-stacked DRAMs suffer from a significant loss of refresh power, which is solely required to maintain data. Although various schemes have been proposed to mitigate this issue, they cannot be adopted by commercial products due to compatibility issues. To tackle this issue, we propose EXTREME, which effectively reduces the refresh power of 3D-Stacked DRAMs. In order to retain the compatibility with OS, a simple page table manager is implemented at the logic die of 3D-stacked DRAM devices, which pins the page table to a specific memory space. The experiment results demonstrate that this reduces the refresh power at idle time by up to 98 percent with 16 KB of SRAM (static RAM) and 64 KB of DRAM register overhead for a 2 GB 3D-stacked DRAM device. Ho Hyun Shin, Young Min Park, Duheon Choi, Byoung Jin Kim, Dae-Hyung Cho, Eui-Young Chung |
IEEE Trans. Computers | 2 |
| 2018 | ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices
JuHyung Hong, Sangwoo Han, Young Min Park, Eui-Young Chung |
IEEE Trans. Very Large Scale Integr. Syst. | 3 |