Matched circuit components are crucial for maximum efficiency in radio frequency (RF) systems, necessitating accurate load impedance monitoring. This paper proposes a method using reference point optimization with periodic structures for precise, low-overhead impedance measurements suitable for Built-in Self-Test (BIST). The novel technique uses a linear matching network and voltage detectors to sense load variations. A periodic structure measures voltages, and a multi-step algorithm selects optimal reference points to determine the load impedance.

Within the space electronics industry, several strategies have been implemented to mitigate heavy ion, neutron, and proton induced radiation effects in CMOS processes, including radiation through process technology alterations and through circuit design, layout, and architecture. In this work, a new method is proposed that adaptively calibrates integrated analog circuits in CMOS bulk technology through bias tuning to create a radiation hardened system. In this technique, the device parameters that vary due to total ionizing dose radiation are monitored using built-in-self-test circuitry. These monitored parameters are used to tune and calibrate circuit level performance parameters. This work analyzes the TID radiation induced performance shifts in three critical power management circuits and uses bias tune in each circuit to recover circuit performance. The three circuits include: a ring oscillator, a bandgap voltage reference, and a non-overlap (dead-time) clock generator.

This work proposes a novel design automation (DA) technique that uses a multifaceted approach combining Multivariate Regression with Geometric Programming (GP) to design analog circuits. Previous DA methods employing GP have typically used analytical derivations of the various design equations representing an analog circuit. The proposed DA method eliminates the need for analytical derivations by using simulation data and multivariate regression to generate statistical models combined with GP to solve these statistical expressions with respect to optimum circuit design parameters. This presented statistical GP method has been applied to successfully design a five-transistor two-stage operational amplifier and a folded cascode amplifier in a TSMC 65nm CMOS technology. The presented statistical GP DA results are comparable to the design results obtained from both analytical GP and manual design by an experienced analog design engineer.

This work presents a galvanically isolated chip-to-chip communication system that utilizes laterally coupled resonators in combination with a new differential full-wave receiver architecture. Lateral resonant coupling increases the isolation capability and significantly minimizes the intra-chip coupling capacitance of galvanic isolators beyond the limits of vertical coupling in standard CMOS. The presented system marries the merits of a laterally resonant coupled channel with a source-gate coupled low-power, low-latency RF detector architecture that enables high common-mode and differential noise immunity. A center-tapped transformer is used as the interface between the proposed fully differential receiver and the communication channel to further enhance the common-mode transient immunity (CMTI). The proposed system is integrated in a$0.25~\mu \text{m}$CMOS process with four metal layers and does not alter the native process or necessitate additional fabrication steps. The design does not require exotic packaging and achieves state-of-art CMTI of 650 kV/$\mu \text{s}$at 5 kVpk isolation, sub-20ns propagation delay, and maintains a small form-factor of 0.95 mm2. The GI system exhibits robust performance to fabrication variations, with less than ±0.3% and ±8% sensitivity to process variation and post-assembly chip distance offset, respectively.

There is a growing demand for low-cost and effective test solutions to support state-of-the-art analog and mixed-signal systems that are continuously increasing in complexity and functionality, while decreasing in product cost. This innovative practice session highlights various aspects of design for test (DfT) in high-complexity, analog-dominated systems with three talks that focus on: DfT in power management integrated circuits (ICs), an alternative testing method to analog test bus, and pre-silicon built-in self-test (BIST) verification, where BIST is used to monitor complex mixed-signal systems. These talks will be given by industry experts from Dialog Semiconductor, Xilinx, and Texas Instruments.

Globalized supply chain for electronic circuit manufacturing has reduced the production cost considerably. However, it also presents a challenge since many companies/players contribute to the product and it is not always possible to control or monitor every third-party employee or contractor that takes part in the process. A design house that relies on a foundry for manufacturing needs to ensure that the manufactured devices conform to the agreed-upon process model between the design house and the foundry. Potential deviation from the process model may be due to incidental quality control issues, or due to malicious modifications to the process or circuit layout with the intent of doing harm during in-field operation. In this paper, we present a multivariate methodology to detect even small process and layout level modifications to the circuit by using mission-mode specifications as well as enhanced test modes. We present an algorithm for detecting process/layout modifications and for selection of test inputs to be used in the detection process. Experimental results on an LNA circuit show that the proposed technique can achieve high authentication accuracy even for a single device with a negligible false positive rate.

Internet of Things (IoT) nodes used in environmental monitoring and smart city applications are becoming increasingly prevalent with over $200B projected market potential. These nodes typically employ one-way communications using a high-end transmitter without a corresponding receiver. Testing of such transmitter-only systems poses an additional challenge. Due to the lack of a receiver, low-cost test techniques, such as loop-back, cannot be used. In this paper, we present a low overhead built-in self-test (BIST) technique to characterize imbalances of IQ transmitters without a receiver, both for post-production and in-field test purposes. The proposed BIST uses simple circuitry and a single test setup. The target parameters are analytically computed independent from internal BIST parameters which eliminates the need for initial calibration phase. All measurements are in DC and no external RF signal generation is required. The overall measurement time, including the computation time, is less than 2ms. Simulation and measurement results show that the proposed method provides adequate estimation accuracy for digital calibration.

This article presents a Built-in self-test (BIST) solution for polar transceivers with low cost and high accuracy. Radio frequency (RF) Polar transceivers are desirable for portable devices due to higher power efficiency compared to traditional RF Cartesian transceivers. Unfortunately, their design is quite challenging due to substantially different signal paths that need to work coherently to ensure signal quality. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude. In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion, which leads to violation of spectral mask requirements. Typically, these parameters are not directly measured but calibrated through spectral analysis using expensive RF equipment, leading to lengthy and costly measurement/calibration cycles. However, characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. In this article, we propose a technique to measure with the intent to calibrate impairments of the polar transceiver in the loop-back mode. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments accurately.

Wireless Revolution V.2 in the form of Internet of Things (IoT) necessitates development of RF on rapidly evolving manufacturing processes using a small team of engineers. These processing nodes are tuned for digital performance and typically present with higher process variations. Manufactured RF devices either need to include larger margins to guarantee performance or be tuned post-manufacture to recover the performance. In this paper, we present a set of design principles for RF devices that can be adapted post-production for specific needs of the target application. Post-production tuning lifts the design burden from engineering efforts to measurement and calibration at the production test time.

The RF Power Amplifier (PA) is usually the bottleneck in designing high efficiency, high linearity wireless transceivers within any given power specification. Pico-cell basestation PAs deliver power in the range of 10 Watts, with aggressive gain and efficiency requirements for next generation cellular networks. The slightest variations in PA biasing or the input and output load networks can cause significant degradation in RF PA performance. This work discusses the impact of process variation and variability in input/output networks on RF performance, and suggests ways to regain various performance parameters through post fabrication tuning of the PA.

Built-in Self-Test (BIST) is essential, particularly for radio frequency (RF) devices where off-chip RF signal analysis is costly or in some cases, infeasible. Two major problems have made RF BIST elusive. First, process variations make the BIST circuit behavior hard to predict, limiting accuracy of measurements. Second, the overhead, particularly in terms of performance degradation, make RF BIST undesirable. In this paper, we address these two issues for RF BIST gain measurement. First, we show that by setting up relative gain measurements and carefully crafting the BIST methodology and the matching BIST circuit, the effect of process variations on measurement accuracy can be suppressed. Second, by co-designing the BIST circuit together with the device under test (DUT), performance impact can be eliminated or significantly reduced. To demonstrate the proposed approach, we design a low noise amplifier (LNA) as the DUT together with the BIST circuit. We also design a stand-alone LNA with the same specifications and manufacture these two circuits on the same die. We show that the LNA gain can be determined very accurately, using only DC measurements, and the performance impact of the BIST circuit is negligible.

Failure due to aging mechanisms in CMOS devices is an important concern of RF circuits. Lifetime of analog/RF circuits is defined as the point where at least one specification will fail due to aging effects. In this brief, we present a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices and inductors at design time (presilicon). We identify reliability hotspots and concentrate on these circuit components to enhance the lifetime with low area and no performance impact.

We propose a self-test method for zero-IF radio frequency transceivers using primarily loopback, aided by a small built-in self-test (BIST) circuitry, to determine critical performance parameters, such as I/Q imbalance and nonlinearity coefficients. The transceiver is placed in the loopback mode by couplers, specifically designed to be asymmetric with respect to the primary path and the BIST path. The loopback path is also designed to include two traces with slightly different delays to enable parameter deembedding. Transceiver parameters are analytically computed using baseband I and Q signals over two frames, each of which is 200 μs in duration. Overall, measurement time is <;10 ms, including computation time. In addition to loopback hardware support and the associated parameter deembedding methodology, we propose a complimentary BIST circuit to measure the transmitter (TX) gain. The measured parameters can be used for predistortion or postdistortion to calibrate the transceiver, both at production time and in the field. Both simulation and hardware measurement results show that the proposed method can determine the target performance parameters with adequate accuracy for digital calibration. Measurement and the subsequent calibration are shown to reduce TX error vector magnitude more than fivefold, even for significantly impaired systems.

RF Built-in-Self-Test requires generation and analysis of high frequency signals on-chip, which usually involves complex circuitry. Generally a high frequency to low frequency conversion, such as a peak or amplitude detector, is employed to analyze the output of the device under test (DUT). However, this conversion circuit is subject to similar process variations as the DUT, which has to be included in the measurement process. Moreover, despite affecting the accuracy of the entire measurement, the input generation for RF BIST is sparsely discussed. While relative measurements, such as gain, can be made without knowing the input signal attributes, other parameters, such as output power, IIP3, or IIP5 require absolute measurements, hence the knowledge of the input signal amplitude. In this paper, we propose a technique for on-chip amplitude measurement that is independent of process variations. The approach relies on on-chip generation of a square wave using an RF limiter with two different amplitudes. Using these two input signals and mathematical modeling, we extract the amplitude at the output of the DUT with high accuracy. The circuits for the BIST have been designed and simulated at the transistor level, including process variations. The concept of the proposed measurement technique is demonstrated in hardware using off-the-shelf components.

An RF Phased array can steer the direction of the beam electronically and it brings about benefits in terms of signal to noise ratio (SNR) and directivity. However, testing the phased array generally requires expensive and high performance RF equipment. This increases production test cost and hampers in-field calibration. We present a low-cost, self-compensating Built-In Self-test (BIST) and calibration solution for RF phased arrays. In our proposed method, we apply a sinusoidal test signal with unknown amplitude to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. The BIST circuits are designed and post layout simulations are performed with within-die and die-to-die process variations. Simulations confirm that the BIST circuit provides very accurate results without having to know sinusoidal signal amplitudes or the relation between them. Furthermore, a prototype four-element phased-array PCB was designed and fabricated for verifying our proposed method. With the proposed method, the phase difference between elements can be measured and calibrated with less than 1° error, which would allow for self-monitoring in 6-bit phased array applications.