Electrowetting-on-dielectric (EWOD) chips have emerged as popular actuators for droplet-based digital microfluidic biochips. The chip-level design of EWOD chips allows for the integration electrode addressing and wire routing, thus helping cope with the increasing complexity of biochemical assays. Furthermore, high-frequency EWODs also facilitate finishing time-sensitive bioassays such as incubation and emerging flash chemistry in specific time periods. However, the reliability of the EWOD chip is reduced by the contact angle change reduction problem as a result of the repeated and frequent switching of electrodes. Thus, the chip-level design of EWOD chips should consider reliability, electrode addressing, and the wire routing problem. This paper presents a graph-based chip-level design algorithm. By setting the switching-time constraint, the number of switching times can be limited to minimize the impact of the contact angle change reductions problem. Also, a progressive addressing and routing approach is proposed to overcome the complex wire routing problem. Experimental results show the proposed algorithm effectively minimizes the impact of the contact angle change reduction problem, thus providing a reliable chip-level design with a feasible wire routing solution with the required number of pins.

Nowadays, electrowetting-on-dielectric (EWOD) chips have become the most popular actuator for droplet-based digital microfluidic biochips. As the complexity of biochemical assay increases, the chip-level design of EWOD chips which integrates electrode addressing and wire routing are widely adopted. Furthermore, to finish many time-sensitive bioassays such as incubation and emerging flash chemistry in a specific time, a high-frequency EWOD is used to satisfy the demand. However, the reliability of the EWOD chip degrades due to the contact angle reduction problem incurred by huge number of switching times of an electrode. Thus, the reliability issue, electrode addressing, and wire routing problem should be considered together in the chip-level design of an EWOD chips. In this paper, a graph-based chip-level design algorithm is presented. By setting the switching-time constraint, the number of switching times can be limited to minimize the impact of contact angle reductions problem. Also, a progressive addressing and routing approach is proposed to overcome the challenge of complex wire routing problem. Experimental results show that the influence of contact angle reduction problem can be effectively minimized by proposed algorithm. A reliable chip-level design with feasible wire routing solution can be generated with number of pins are satisfied.

Electrowetting-on-dielectric (EWOD) chips have become the most promising technology to realize pin-constrained digital microfluidic biochips (PDMFBs). Reliability is a critical factor in the design flow of EWOD chips, it directly affects the execution of bioassays. The trapped charge problem is the major factor degrading chip reliability, and this problem is induced by excessive applied voltage. Nevertheless, to comply with the pin constraint for PDMFBs, signal merging is inevitably involved, and thereby incurring trapped charges due to unawareness of the applied voltage. Except for the trapped charge problem, the wire routing required to accomplish electrical connections increases the design complexity of pin-constrained EWOD chips. However, previous research has failed to address the problems of excessive applied voltage and wire routing. Therefore, the resulting chip is more likely to fail during execution or cannot be realized because of the wire routing problem. A network-flow-based algorithm for reliability-driven pin-constrained EWOD chips is presented in this paper. The proposed algorithm not only minimizes the reliability problem induced by signal merging, but also prevents the operational failure caused by inappropriate addressing results. The proposed algorithm also provides a comprehensive routing solution for EWOD chip-level designs. The experimental results demonstrate the effectiveness of the proposed algorithm on real-life chips.