In the context of NextG Wireless Networks, addressing the challenges of wireless communication link reliability is paramount to ensure efficient Distributed Learning systems. However, many recent solutions have overlooked key challenges, such as packet-level losses and the impact of TCP retransmissions, which are crucial for the robustness of these systems. In this paper, we propose the integration of fountain codes into the distributed learning process to offer a robust mechanism to counteract packet loss. Specifically, we propose a cumulative strategy logic based on fountain codes specifically tailored for packet exchanges in Distributed Learning applications. Our evaluation shows that fountain codes significantly enhance the efficiency and reliability of distributed learning model updates under severe packet loss conditions, e.g., a packet reduction of ≈ 84% (≈ 60%) at the UE (gNB) side compared to traditional TCP methods when packet loss probability reaches 0.9 in Federated Learning context. However, under low packet loss scenarios, fountain codes computational overhead becomes non-negligible. These results highlight the potential of fountain codes to serve as a robust alternative to conventional communication protocols in distributed learning systems, particularly in environments characterized by unstable network conditions.

NextG wireless will heavily rely on Federated Learning (FL) applications to learn context-aware AI solutions from the massive amount of generated data. Ensuring the reliability of wireless links for such applications is paramount, especially for FL where packet loss can severely hamper performance and efficiency. Traditional approaches fall short under the high packet loss characteristics of wireless networks. This demo shows how the integration of Fountain Codes (FC) into the FL process can bring notable improvements in packet transmission efficiency, especially under high packet loss conditions.

Ultra Reliable Low Latency Communications (URLLC) scenarios require very low latency and high reliability, imposing an optimization of every aspect of 5G data processing, transmission, and networking. Artificial Intelligence (AI)-based tools can be helpful resources in this context, enhancing multiple functionalities, from network resource allocation to network security. In this paper we propose a solution placed at the next generation eNB (gNB)-Central Unit (CU) level, relying on Neural Networks (NNs), capable of classifying incoming packets. The developed system increases the security of 5G and B5G architectures, protecting the 5G Core (5GC) from potential attacks. To comply with URLLC requirements on latency, we present an architecture leveraging photonic hardware to speed-up NN computations. The proposed solution, namely Photonic-Aware Neural Network (PANN), complies with physical layer constraints raised by photonic analog computing and can achieve high throughput and time-of-flight latency. The classification performance of the devised PANN model has been assessed through simulation on the distilled Kitsune dataset, suited for 5G scenarios. The experiments proved that PANN significantly lowers the chance of transmitting malicious packets to the 5GC with a classification performance increasing with the bit resolution supported by the analog photonic physical layer.

Abstract Photonics-based neural networks promise to outperform electronic counterparts, accelerating neural network computations while reducing power consumption and footprint. However, these solutions suffer from physical layer constraints arising from the underlying analog photonic hardware, impacting the resolution of computations (in terms of effective number of bits), requiring the use of positive-valued inputs, and imposing limitations in the fan-in and in the size of convolutional kernels. To abstract these constraints, in this paper we introduce the concept of Photonic-Aware Neural Network (PANN) architectures, i.e., deep neural network models aware of the photonic hardware constraints. Then, we devise PANN training schemes resorting to quantization strategies aimed to obtain the required neural network parameters in the fixed-point domain, compliant with the limited resolution of the underlying hardware. We finally carry out extensive simulations exploiting PANNs in image classification tasks on well-known datasets (MNIST, Fashion-MNIST, and Cifar-10) with varying bitwidths (i.e., 2, 4, and 6 bits). We consider two kernel sizes and two pooling schemes for each PANN model, exploiting $$2\times 2$$ 2 × 2 and $$3\times 3$$ 3 × 3 convolutional kernels, and max and average pooling, the latter more amenable to an optical implementation. $$3\times 3$$ 3 × 3 kernels perform better than $$2\times 2$$ 2 × 2 counterparts, while max and average pooling provide comparable results, with the latter performing better on MNIST and Cifar-10. The accuracy degradation due to the photonic hardware constraints is quite limited, especially on MNIST and Fashion-MNIST, demonstrating the feasibility of PANN approaches on computer vision tasks.

The Open Computing Language (OpenCL) is increasingly adopted for programming processors with reconfigurable hardware acceleration. The 5G telecommunication infrastructure, imposing strong latency constraints on the managed communications, may benefit from OpenCL-designed accelerated processing. This paper presents the first study to evaluate OpenCL hardware acceleration in the context of a 5G base station physical layer. The implementation and optimization process to accelerate the Orthogonal Frequency Division Multiplexing (OFDM) part of the 5G downlink is conducted on a high-end Field Programmable Gate Array (FPGA). We show that the proposed OpenCL implementation complies with the 5G processing timing requirements since the computation time is consistent with the present 5G deployment. However, to be suitable for 5G, the OpenCL platform must improve the data latency transfer between hardware and software. Moreover, a further enhancement for the OpenCL implementation is to improve the code by means of OpenCL optimization techniques. In this way, the performance can be further improved with respect to optimized software on vectorized high-end processors.

Current trends in high performance and embedded computing include design of increasingly complex hardware architectures with high parallelism, heterogeneous processing elements, and nonuniform communication resources. In order to take hardware and software design decisions, early evaluations of the system nonfunctional properties are needed. These evaluations of system efficiency require electronic system-level information on both algorithms and architecture. Contrary to algorithm models for which a major body of work has been conducted on defining formal models of computation (MoCs), architecture models from the literature are mostly empirical models from which reproducible experimentation requires the accompanying software. In this paper, a precise definition of a model of architecture (MoA) is proposed that focuses on reproducibility and abstraction and removes the overlap previously existing between the notions of MoA and MoC. A first MoA, called the linear system-level architecture model (LSLA), is presented. To demonstrate the generic nature of the proposed new architecture modeling concepts, we show that the LSLA model can be integrated flexibly with different MoCs. LSLA is then used to model the energy consumption of a state-of-the-art multiprocessor system-on-chip (MPSoC) when running an application described using the synchronous dataflow MoC. A method to automatically learn LSLA model parameters from platform measurements is introduced. Despite the high complexity of the underlying hardware and software, a simple LSLA model is demonstrated to estimate the energy consumption of the MPSoC with a fidelity of 86%.

Softwarization is a systemic trend which appears under several paradigms impacting networks, services and terminals evolution. Even the Internet of Things (IoT) scenario is going to be affected by this revolution. The efforts that are being made to provide IoT objects with embedded logic reconfiguration capabilities and the architectures that are being defined to support standard Machine-2-Machine (M2M) transactions are clear expressions of this trend. In this direction, a powerful framework to enable softwarization in constrained IoT objects is T-Res, where a virtual-machine based design is used to support execution tasks abstraction. To adopt T-Res in a real scenario in which device software functionalities can be remotely managed in an automatic fashion, its integration in a global M2M architecture must be defined. In this paper, the integration of TRes in the oneM2M architecture is presented, and its feasibility concerning application logic execution time and power consumption is analyzed by taking into account new generation devices. Performance results show that although oneM2M compliant TRes requires greater execution times and energy consumption when compared to a monolithic firmware approach, it results to be a feasible solution to be implemented in current and next generation IoT objects in order to provide advanced application logic reconfigurability features in softwarized ecosystems.

Industrial Wireless Sensor Networks (IWSNs) are nowadays becoming more and more popular thanks to their flexibility and pervasive monitoring capabilities to support process automation and remote maintenance applications. In such a scenario, channel errors due to the wireless medium can result in data packet losses, and consequently in unreliable IWSN services. To mitigate the above reported problem, this paper presents a lightweight error correction scheme specially developed for IEEE802.15.4-based IWSNs. By adding error correction and detection information inside the IEEE802.15.4 MAC data frame, the proposed FEC scheme is able to guarantee a backward compatibility with the standard while providing advanced capabilities in recovering data packets affected by bit errors. In the paper the benefits of the proposed technique are first evaluated through simulated loss traces, then they are validated in a real environment by considering real loss traces collected in an electricity power plant. The proposed error correction scheme is able to recover around 50% of the data packets that would be lost in case of a standard communication without any error correction capability.

In this letter, we propose HOG-Dot, a method for the direct computation of the polar image gradients coordinates from the pixels values. The proposed algorithm, to be used as the first step of the Histogram of Oriented Gradient (HOG) pipeline, approximates the exact gradient with its projection onto a versor chosen among the projection plane set. Instead of non linear computations, the HOG-Dot method exploits linear operations while introducing a bounded approximation error with respect to other HOG approaches, thus resulting a more suitable solution for embedded devices. Concerning the state of the art, it also achieves improved accuracy with the mathematical spatial gradient formulation .