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Jared A. Beekman

dblp:143/6212 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Interconnection networks and networks-on-chip · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis		 0.011987
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation · DAC 1987
Electronic design automation › logic synthesis
multilevel logic synthesis		 0.011987
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation · DAC 1987
Interconnection networks and networks-on-chip › interconnection networks
rectangular mesh		 0.011987
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation · DAC 1987

Methods — techniques the papers use, named apart from their topics

recursive enumeration · 0.0
YearPublicationVenuePosition
1987 Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation
abstract
This paper introduces a standard structure for VLSI design which we call the mesh array and describes a design tool called LOGICIAN which minimizes a set of functions for realization in CMOS mesh arrays. LOGICIAN features multi-level logic synthesis through recursive enumeration of each function. Several techniques to speed-up the minimization process in LOGICIAN are described.
Jared A. Beekman, Robert Michael Owens, Mary Jane Irwin
 DAC1