Software-Defined Networking (SDN) leverages centralized control to enhance network flexibility, programmability, and resource management. However, this centralization also makes it susceptible to Distributed Denial of Service (DDoS) attacks. In this attack, both compromised hosts and malicious third-party applications flood the controller with fake requests, causing network disruptions and potential failures. Existing literature lacks a comprehensive solution that effectively addresses both compromised host-based and application-layer DDoS attacks. Additionally, there is no mitigation mechanism capable of blocking malicious traffic directly at its source. To address this limitation, we propose DDoSBlocker which is a protocol-independent and lightweight DDoS defense mechanism against multi-layer DDoS attacks in SDN. It consists of three essential modules. The first module identifies the source points of compromised hosts responsible for DDoS attacks by leveraging time-based mapping technique integrated with machine learning technique. The second module detects malicious third-party applications by analyzing their application IDs using a machine learning approach with six novel features. Finally, the last module implements a mitigation strategy that effectively blocks malicious traffic at its source, ensuring minimal impact on legitimate network operations. DDoSBlocker is deployed in the Floodlight controller, and its effectiveness is assessed across multiple network scenarios. Our experimental results demonstrate that DDoSBlocker successfully detects and mitigates various types of DDoS attacks while achieving a 25–53% reduction in False Positive Rate (FPR) compared to existing approaches.

Frequent and inconsistent main-memory requests in large-scale Network-on-Chip (NoC) systems pose significant performance challenges. While strategies like multi-level cache hierarchies and network resource optimization mitigate memory bottlenecks, their impact on the statistical predictability of memory access remains underexplored.We propose a structured methodology to guide the design of NoC-based systems by balancing the tradeoff between the statistical predictability of memory access and the average throughput of the memory controller (MC). Using Power Spectral Density (PSD) of inter-packet arrival times (IPAT) at MC, we evaluate the impact of key architectural parameters, cache size, buffer size, and network size on memory access predictability. We analyze changes in PSD characteristics, including stationarity, monofractal chaos, and multifractal chaos, alongside average MC throughput to identify optimal parameter values that maximize both predictability and throughput. Our results demonstrate that fine-tuning these parameters can alleviate chaoticity in IPAT at MC, thereby providing a valuable framework for designing efficient NoC-based systems across diverse applications.

Most complex cooperative systems, such as networks on chip (NoCs), possess self-organizing properties and exhibit fluctuations in data traffic with similar statistical characteristics across multiple timescales, a.k.a., scaling behavior. Abrupt transitions in the scaling behavior of these fluctuations, caused by spikes in data traffic, network congestion, etc., indicate instability in the queueing dynamics of NoC routers. This instability hampers the predictability of real-time flow control mechanisms, leading to unpredictable delays and communication failures. Detecting and mitigating these instabilities or phase transitions is crucial in domains requiring stability and real-time control, such as aviation and healthcare. In this paper, we propose a real-time monitoring and characterization strategy for data traffic from influential routers to identify and mitigate impending instabilities before their onset. Leveraging the self-organization characteristic of NoCs, we propose to implement targeted mitigation on influential nodes to achieve network-wide effects. We demonstrate the effectiveness of our strategy on various benchmarks by comparing traffic analysis plots before and after mitigation. Our results show that the proposed phase transition mitigation improves the network performance by an average of 39.6% and buffer utilization by an average of 4.62%.

Increasing complexity in power management (PMT) has led to a growing demand for third-party power managers (3PPMs) in Network-on-Chip based Mixed-Critical Systems (NoCMCS). However, a malicious 3PPM can exploit the interdependence of power amongst the router nodes to orchestrate well-structured, covert power attacks. Detection and localization of a malicious 3PPM is crucial to restore standard dynamic PMT and mitigating system performance degradation. We propose a novel, non-invasive, low-overhead, attack detection and localization framework for Hardware Trojan (HT)-assisted intermittent power attacks with random activation and deactivation phases in NoCMCS. In Phase-I, our framework makes use of pre-profiled thermal statistics of router nodes to detect any anomaly at runtime. In Phase-II, it leverages a self-aware methodology to locate the router nodes with malicious 3PPM. The proposed framework can detect multiple intermittent HTs in the network. Experimental evaluations on real-life benchmarks show that Phase-I of our framework is able to consolidate the search space of malicious nodes, reducing almost 90% of Phase-II’s computational workload. Phase-II localizes the malicious router nodes across various experimental scenarios with zero false positives. We also demonstrate the robustness of our framework for detecting and localizing malicious router nodes for different intermittent HTs with varying burst attacks over time.

Despite numerous studies on dwindling groundwater resources in northern India, the linkage between Groundwater Storage (GWS) and hydroclimatic variability in the Indo-Gangetic Plain (IGP) has not been widely studied. In this regard, an attempt has been made to assimilate the satellite-based observations of hydroclimatic variables (predictors) (Precipitation- P, Evapotranspiration- ET, Soil Moisture-SM, and Runoff- RO) to predict GWS using multi-regression machine learning models (Random Forest; R2=0.81). Predicted estimates of the GWS show that northern and NW parts of the IGP are highly affected, and large residual estimates in the eastern parts are due to the uncertainty in the observed P and ET. Despite the performance of the models, spatial biases have been recognized between the observed and predicted estimates of the GWS, suggesting no significant variations among the predictors (hydroclimatic variables) in the major parts of the study area.

Wireless Network-on-Chip (WNoC) requires a Medium Access Control (MAC) mechanism for an interference-free sharing of the wireless channel. In traditional MAC, a token is circulated among the Wireless Interfaces (WIs) in a Round Robin manner. The WI with the token holds the channel for a fixed number of cycles. However, the channel requirement of the individual WIs dynamically changes over time due to the varying traffic density across the WNoC. Moreover, the conventional WNoCs give equal importance to all the traffic taking the wireless path and transmit it in an oldest-first manner. Nevertheless, the critical data can degrade the system performance to a large extent by delaying the application runtime if not served promptly. We propose 2DMAC, which can change the token arbitration pattern and tune the channel hold time of each WI based on its runtime traffic density and criticality status. Moreover, 2DMAC prioritizes the critical traffic over the non-critical traffic during the wireless data transfer. The proposed mechanism improves the wireless channel utilization by 15.67% and the network throughput by 29.83% and reduces the critical data latency by 29.77% over the traditional MAC.

Shared memory architectures, as opposed to private-only memories, provide a viable alternative to meet the ever-increasing memory requirements of multi-accelerator systems to achieve high performance under stringent area and energy constraints. However, an impulsive memory sharing degrades performance due to network contention and latency to access shared memory. We propose the Accelerator Shared Memory (ASM) framework to provide an optimal private/shared memory configuration and shared data allocation under a system’s resource and network constraints. Evaluations show ASM provides up to 34.35% and 31.34% improvement in performance and energy, respectively, over baseline systems.

Wireless Network-on-Chip (WNoC) broadly adopts single channel for low overhead data transmission. Sharing of the channel among multiple wireless interfaces (WIs) is controlled by a channel access mechanism (CAM). Such CAM can be malfunctioned by a Hardware Trojan (HT) in a malicious WI or a rogue third party intellectual property (IP) core present on the same System-on-Chip (SoC). This may result in denial-of-service (DoS) or spoofing in WNoC leading to starvation of healthy WIs and under-utilization of wireless channel. Our work demonstrates possible threat model on CAM and proposes low overhead decentralized countermeasures for both DoS and spoofing attacks in WNoC.

Deep convolution neural networks (CNNs) are computationally intensive machine learning algorithms with a large amount of data that impose various challenges for their hardware implementation. To meet the high computing demands of CNNs, many accelerator designs are proposed that revolve around achieving high parallelization, increasing on-chip data reuse and efficient memory hierarchy, etc. However, very few works have attempted to address the communication challenges in these massively parallel accelerators architectures, which is the most anticipated performance bottleneck. Traditional interconnections like bus, crossbar and even Network-on-Chip ( N o C) topologies like mesh fail to achieve the peak performance required by the large number of processing elements on accelerators. In this work, we address the communication bottlenecks of accelerators by extensively studying the application data-flow. We propose an efficient accelerator architecture that employs broadcast enabled low latency wireless links along with traditional wired links to efficiently support the data-flow of accelerators and achieve high communication performance. Evaluation of the proposed design shows that it achieves 28 % latency reduction, 19x bandwidth improvement and 35% network energy saving as compared to baseline wired networks.

Wireless Network-on-Chip (WNoC) has been proposed to overcome long-distance communication bottlenecks of wired NoCs. Token passing mechanism has generally been adapted to allocate the wireless channel among Wireless Interfaces (WIs). In this work, we propose a comparator based controller to provide a flexible and efficient channel allocation scheme. It utilizes a comparator attached to the antenna, along with modifications to header flit to perform channel allocation along with power gating WIs to save energy. Evaluation of proposed scheme on CPU/GPU system shows 53% reduction in token passes and 9% energy saving as compared to timer based approach.