This work presents a single-stage operational transconductance amplifier (OTA) with high DC gain for driving nano-farad capacitive loads. The circuit employs two conjugated current mirrors to form high-impedance nodes, enhancing transconductance and driving capability. Flipped-voltage follower (FVF) cells act as variable tail current sources to boost transconductance and generate a dynamic current larger than the bias current during slewing, enabling a faster transient response. The FVFs also allow additional folded drivers on the cascode stage for further improvement. To integrate these techniques, both n- and p-channel differential pairs are used at the input. Implemented in TSMC 0.18-μm CMOS, the OTA achieved a simulated DC gain above 100 dB and a measured gain of 95 dB, validating the proposed design. It shows a unity-gain bandwidth of 5.85 MHz and a slew rate of 0.347 V/μs while driving a 2×4 nF load at 1.8 V.

Analog computing at the edge is an emerging strategy to limit data storage and transmission requirements, as well as energy consumption, and its practical implementation is in its initial stages of development. Translating properties of biological neurons into hardware offers a pathway towards low-power, real-time edge processing. Specifically, resonator neurons offer selectivity to specific frequencies as a potential solution for temporal signal processing. Here, we show a fabricated Complementary Metal-Oxide-Semiconductor (CMOS) mixed-signal Resonate-and-Fire (R&F) neuron circuit implementation that emulates the behavior of these neural cells responsible for controlling oscillations within the central nervous system. We integrate the design with asynchronous handshake capabilities, perform comprehensive variability analyses, and characterize its frequency detection functionality. Our results demonstrate the feasibility of large-scale integration within neuromorphic systems, thereby advancing the exploitation of bio-inspired circuits for efficient edge temporal signal processing.

This work presents an ultralow-voltage and ultralow-power current-mode delta-sigma modulator designed for biomedical applications. To implement both the integrator and quantizer of the modulator, a bulk-driven current conveyor circuit is introduced. By satisfying the Barkhausen criterion, the proposed modulator can intrinsically oscillate, producing a pulse-density modulated (PDM) output. This clock-less operation avoids conventional quantization noise associated with discrete-time sampling. The current-mode design not only provides improved matching properties and a wider bandwidth but also simplifies the implementation of passive components, resulting in a smaller silicon area compared to voltage-mode modulators—though this area efficiency is partly achieved using off-chip components. The circuit has been fabricated using standard TSMC 0.18-$\mu $m CMOS technology, occupying a silicon area of$226~\mu $m×$264~\mu $m. Despite consuming only 34 nW of power, experimental results demonstrate a signal-to-noise and distortion ratio of 57.1 dB, corresponding to an effective resolution of 9.2bits with a bandwidth of 81 Hz. Additionally, the use of the bulk-driven method achieves an input dynamic range of ±24nA under a supply voltage of 0.3 V.

The Softmax activation function plays a pivotal role in both the attention mechanism of Transformers and in the final layer of neural networks performing classification. The Softmax function outputs probabilities by normalizing the input values, emphasizing differences among them to highlight the largest values. In digital implementations, the complexity of softmax grows linearly with the number of inputs. In contrast, analog implementations enable parallel computations with lower latency. In this work, we demonstrate that this approach achieves a more efficient linear scaling of latency as vector size increases logarithmically. This analog softmax circuits are implemented in TSMC 28 nm PDK technology, capable of driving up to 128 inputs and producing an analog current output spanning three orders of magnitude. The study examines the circuit’s power consumption, latency, and error, emphasizing its efficiency compared to the alternative approach of converting outputs to digital signals via ADCs and performing the softmax calculation digitally. By reducing reliance on these power-intensive operations, this work aims to significantly enhance energy efficiency in in-memory computing systems.

The non-destructive capacitance read-out of ferroelectric capacitors (FeCaps) based on doped HfO2metal-ferroelectric-metal (MFM) structures offers the potential for low-power and highly scalable crossbar arrays. This is due to a number of factors, including the selector-less design, the absence of sneak paths, the power-efficient charge-based read operation, and the reduced IR drop. Nevertheless, a reliable capacitive readout presents certain challenges, particularly in regard to device variability and the trade-off between read yield and read disturbances, which can ultimately result in bit-flips. This paper presents a digital read macro for HfO2FeCaps and provides reliability analysis for the capacitive readout of HfO2FeCaps, taking device variability and yield challenges into account. An experimentally calibrated physics-based compact model of HfO2FeCaps is employed to investigate the reliability of the read-out operation of the FeCap macro through Monte Carlo simulations. Based on this analysis, we identify limitations posed by the device variability and propose potential mitigation strategies through design-technology co-optimization (DTCO) of the FeCap device characteristics and the CMOS circuit design. Finally, we examine the potential applications of the FeCap macro in the context of secure hardware. We identify potential security threats and propose strategies to enhance the robustness of the system.

The ability to detect correlated events in the environment is an important feat of biological neural networks. Neuromorphic computing strives to mimic this ability for efficient sensory processing. For this purpose, we propose a HfO2-based ferroelectric capacitor (FeCap)-complementary metal oxide semiconductor (CMOS) leaky integrate-and-fire (LIF) neuron able to detect highly correlated events exploiting two different temporal dynamics. The possibility to exploit two time constants increases the versatility of the neuron and its dynamic adaptation while offering a compact and elegant solution for detection of both transient and sustained coincidences. Moreover, the time constants are in biologically relevant time scales, which makes the neuron suitable to solve real-time tasks such as keyword spotting or sensory processing. The proposed FeCap-based LIF (FeLIF) neuron enriches the dynamic of a standard LIF neuron fostering the development of advanced event-based analog neuromorphic hardware.

Novel non-volatile memory devices based on ferroelectric thin films represent a promising emerging technology that is ideally suited for neuromorphic applications. The physical switching mechanism in such films is the nucleation and growth of ferroelectric domains. Since this has a strong dependence on both pulse width and voltage amplitude, it is important to use precise pulsing schemes for a thorough characterization of their behavior. In this work, we present an on-chip 120 dB programmable range pulse generator, that can generate pulse widths ranging from 10 ns to 10 ms ± 2.5% which eliminates the RLC bottleneck in the device characterisation setup. We describe the pulse generator design and show how the pulse width can be tuned with high accuracy, using Digital to Analog converters. Finally, we present experimental results measured from the circuit, fabricated using a standard 180 nm CMOS technology.

Ferroelectric tunneling junctions (FTJ) are considered to be the intrinsically most energy efficient memristors. In this work, specific electrical features of ferroelectric hafnium-zirconium oxide based FTJ devices are investigated. Moreover, the impact on the design of FTJ-based circuits for edge computing applications is discussed by means of two example circuits.

In recent years, biologically inspired systems, which emulate the nervous system of living beings, are becoming more and more requested due to their ability to solve ill-posed problems such as pattern recognition or interaction with the external environment. By virtue of their nanoscaled size and their tunable conductance, memristors are key elements to emulate high-density networks of biological synapses that regulate the communication efficacy among neurons and implement learning capability. We propose a TiN/ HfO2/Ti/TiN memristor as artificial synapse for neuromorphic architectures. The device can gradually change its conductance upon application of proper electrical stimuli. More specifically, it features gradual potentiation and depression when stimulated by trains of identical potentiating or depressing spikes, which are easy to be implemented on-chip. Moreover, we demonstrate that the memristor conductance can be regulated according to the delay time between two spikes incoming to the device terminals. This regulation of memristor conductance implements the typical biological learning process named Spike-Time-Dependent-Plasticity (STDP). Finally, collected STDP data were used to simulate a simple fully connected Spiking Neural Network (SNN) for pattern recognition.