Embedded systems are increasingly relying on virtual machines (VMs) to ensure portability and composability of services. To achieve high-performance and resources' isolation, the VM can be mapped to a dedicated core. In shared-memory multi/many cores architectures, the last level cache (LLC) is shared among cores. The state-of-the-art shows that interference on LLC can be a bottleneck for VM's performance. Such interference can depend on several factors, including the design of the applications, guest and host OSes, the hypervisor, and the architecture. Therefore, it is expected that studies analyze in-depth each of these factors. The goal of this work is focusing on the interference that cannot be mitigated by cache isolation techniques supported by the hypervisor, for instance, those caused by host OS applications. Such interference is unpredictable and can jeopardize the performance of the guest. The contribution is a new perspective about how cache interference affects the latency of the guest application and guest OS, crossing different performance metrics in comprehensive plots. We run our experiments on Arm Cortex-A53 processor, and, as guest OS, we employ the state-of-the-art Zephyr OS. Thus, a side contribution is to show Zephyr performance facing cache interference. Our results show that interference on LLC can affect in up to +8 × to slow down the guest application and up to +2.8 ×the subset of kernel functions which are involved for the application execution. Results also show that the guest is mostly affected when its data can fit on the LLC: after this point, the LLC saturation occurs and the host interference becomes insignificant from a guest perspective.

Conventional wired Network-on-Chip (NoC) designs suffer from performance degradation due to multi-hop long-distance communication. To address such a problem, in the past decade, researchers have been focused on investigating Wireless NoC (WiNoC), which evolved as a viable solution to mitigate this communication bottleneck by using single-hop long-range wireless links. However, many researchers reported that these interconnects may suffer failure due to the complexity of implementation. Although few works in the literature tackle faults in WiNoC, none of them provides a comprehensive study related to channel access mechanisms in the presence of faults. To fill this gap, we propose a fault aware WiNoC architecture. We discuss two types of faults in wireless interconnects, namely, transceiver faults and token controller faults. We provide different fault-tolerant techniques to deal with such faults. The proposed FTWiNoC presents, on average, 17.8% and 8.9% improvement in latency compared to two different fault mitigation strategies in the literature.

Many-Core Systems-on-Chip increasingly require Dynamic Multi-objective Management (DMOM) of resources. DMOM uses different management components for objectives and resources to implement comprehensive and self-adaptive system resource management. DMOMs are challenging because they require a scalable and well-organized framework to make each component modular, allowing it to be instantiated or redesigned with a limited impact on other components. This work evaluates two state-of-the-art distributed management paradigms and, motivated by their drawbacks, proposes a new one called Management Application (MA) , along with a DMOM framework based on MA. MA is a distributed application, specific for management, where each task implements a management role. This paradigm favors scalability and modularity because the management design assumes different and parallel modules, decoupled from the OS. An experiment with a task mapping case study shows that MA reduces the overhead of management resources (-61.5%), latency (-66%), and communication volume (-96%) compared to state-of-the-art per-application management. Compared to cluster-based management (CBM) implemented directly as part of the OS, MA is similar in resources and communication volume, increasing only the mapping latency (+16%). Results targeting a complete DMOM control loop addressing up to three different objectives show the scalability regarding system size and adaptation frequency compared to CBM, presenting an overall management latency reduction of 17.2% and an overall monitoring messages’ latency reduction of 90.2%.

In the Software-Defined Networking (SDN) paradigm, routers are generic and programmable forwarding units that transmit packets according to a given policy defined by a software controller. Recent research has shown the potential of such a communication concept for NoC management, resulting in hardware complexity reduction, management flexibility, real-time guarantees, and self-adaptation. However, a centralized SDN controller is a bottleneck for large-scale systems.

Providing quality of service (QoS) for many-core systems with dynamic application admission is challenging due to the high amount of resources to manage and the unpredictability of computation and communication events. Related works propose a self-adaptive QoS mechanism concerned either in communication or computation resources, lacking, however, a comprehensive QoS management of both. Assuming a many-core system with QoS monitoring, runtime circuit-switching establishment, task migration, and a soft real-time task scheduler, this work fills this gap by proposing a novel self-adaptive QoS management. The contribution of this proposal comes with the following features in the QoS management: ( i ) comprehensiveness, by covering communication and computation resources; ( ii ) online, adopting the ODA (Observe, Decide, Act) runtime closed-loop adaptation; and ( iii ) reactive and proactive decisions, by using a dynamic application profile extraction technique, which enables the QoS management to be aware of the profile of running applications, allowing it to take proactive decisions based on a prediction analysis. The proposed QoS management adopts a decentralized organization by partitioning the system in clusters, each one managed by a dedicated processor, making the proposal scalable. Results show that the proactive feature accurately extracts the applications’ profile, and can prevent future QoS violations. The synergy of reactive and proactive decisions was able to sustain QoS, reducing the deadline miss rate by 99.5% with a severe disturbance in communication and computation levels, and avoiding deadline misses up to 70% of system utilization.

The Software-Defined Networking (SDN) is a communication paradigm adopted in computer networking. The SDN assumes simple and programmable routers, removing the control logic from the routers' level, and assigning it to a high-level controller (software), which is responsible for defining the path of the communication flows at run-time. The controller can implement different communication rules to define the paths, as Quality-of-Service (QoS), fault-tolerance, and security. Many-cores may adopt the SDN paradigm due to its advantages: reduced hardware complexity, high reusability, and flexible management of communication policies. However, the challenge to apply the SDN may be the overhead for defining the paths in software against hardware-based approaches. The goal of this paper is to show that SDN can be a viable alternative for NoC management in many-core systems. This work proposes a generic SDN architecture for many-cores, detailing both the hardware and software designs. We compare the quality of the proposal with a state-of-the-art search path mechanism (hardware implemented), in a QoS case-study providing Circuit-Switching (CS) for applications. Results show that the SDN paradigm achieves similar performance than the hardware-based technique regarding path length. Hardware implemented mechanisms present a reduced latency to establish the paths. As the path establishment occurs once for each application flow, results show that the search path latency of SDN is not an actual drawback, as it could be expected.

The workload of many-core systems includes real-time (RT) applications. Obtain energy savings while executing RT applications is a challenge due to the RT timing constraints. The techniques used to reduce the consumption, as dynamic voltage and frequency scaling (DVFS), usually delays the applications, leading to constraint violations. Most works in the literature ensure RT constraints based on design-time analysis of the expected workload by defining the voltage and frequency levels. Our main contribution is the proposal of a Runtime Energy Management for RT applications (RT-REM), using monitored data, and DVFS and task mapping as actuation policies. Supervising the application slack time enables to save energy of RT applications. Evaluations on many-core systems (up to 144 PEs), achieves 18% in energy savings, keeping constraint misses below 2.5%. Our proposal stands out from related works regarding scalability, realistic and accurate energy estimation, and absence of design-time analysis of the application set.

Task migration plays a major role in the implementation of runtime adaptive techniques for many-core systems, as thermal and power management, load balancing, QoS, and fault tolerance. A fast task migration protocol contributes to implementing self-adaptive techniques with low overhead. State-of-the-art proposals still have limitations, with an important impact on the applications' execution time due to the latency to migrate tasks. Aware of the number of simultaneous task migrations required by self-adaptive techniques, this work proposes a low latency tasks migration protocol for many-core systems with distributed memory hierarchy. Our technique eliminates checkpoints, task code replication, enables simultaneous task migrations even in tasks of the same application and parallelizes the task migration with the application execution. These features induce a low latency in the task migration, demystifying the cost to adopt task migration in distributed memory systems. Results compare the proposed approach to the related works.

Large-scale MPSoCs requires a scalable and dynamic real-time (RT) task scheduler, able to handle non-deterministic computational behaviors. Current proposals for MPSoCs have limitations, as lack of scalability, complex static steps, validation with abstract models, or are not flexible to enable changes at runtime of the RT constraints. This work proposes a hierarchical task scheduler with monitoring features. The scheduler is dynamic, supporting changes in RT constraints at runtime. An API enables these features allowing to the application developer to reconfigure the tasks' period, deadline, and execution time by annotating the task code. At runtime, according to the task execution, the scheduler handles the API calls and adjust itself to ensure RT guarantees according to the new constraints. Scalability is ensured by dividing the scheduler into two hierarchical levels: LS (Local Schedulers), and CS (Cluster Schedulers). The LS runs at the processor level, using the LST (Least Slack-Time) algorithm. The CS runs at the cluster level, i.e., a group of processors controlled by a manager processor. The CS receives messages from the LSs, informing the processor slack-time, deadline violations, and RT changes. The CS implements an RT adaptation heuristic, triggering task migrations according to RT reconfiguration or deadline misses. Results show a negligible overhead in the applications' execution time and the fulfillment of the applications' RT constraints even with a high degree of resources sharing, in both processors and NoC.

Current proposals of NoC-based MPSoC adopt an NI (Network Interface) interconnected to a DMA (Direct Memory Access) module to enable the communication between processors through the NoC. The adoption of both modules decouples computation from communication, and a standard interface at the NI provides an abstract way for designers to connect new cores. However, this architecture is inherited from bus-based architectures and can be optimized, by removing unnecessary interfaces, signals, and registers. This paper presents a specialized communication interface for NoC-based MPSoCs, called DMNI (Direct Memory Network Interface). The DMNI merges the functionalities of the DMA and the NI into a single component, directly connecting the NoC router with the processor memory. To avoid stalls in the communication, the design of the DMNI supports simultaneous packet reception and transmission. A simplified and generic programming interface exposes the DMNI services to the software layer. Results show a reduction in the silicon area and performance improvement in the packet transmission.

With the significant increase in the number of processing elements in NoC-based MPSoCs, communication becomes, increasingly, a critical resource for performance gains and quality-of-service (QoS) guarantees. The main gap observed in the NoC-based MPSoCs literature is the runtime adaptive techniques to meet QoS. In the absence of such techniques, the system user must statically define, for example, the scheduling policy, communication priorities, and the communication switching mode of applications. The goal of this paper is to investigate the runtime adaptation of the NoC resources, according to the QoS requirements of each application running in the MPSoC. This paper adopts an NoC architecture with duplicated physical channels, adaptive routing, support to flow priorities and simultaneous packet and circuit switching. The monitoring and adaptation management is performed at the operating system level, ensuring QoS to the monitored applications. The QoS acts in the flow priority and the switching mode. Monitoring and QoS adaptation were implemented in software, resulting in flexibility to apply the techniques to other platforms or include other adaptive techniques, as task migration or DVFS. Applications with latency and throughput deadlines run concurrently with best-effort applications. Results with synthetic and real application reduced in average 60% the latency violations, ensuring smaller jitter and throughput. The execution time of applications is not penalized applying the proposed QoS adaptation methods.

Software development becomes an important issue in today's MPSoC design. Due to the inherent non-deterministic behavior of MPSoCs, they are prone to concurrency bugs. Debugging tools for MPSoC may be grouped in the following classes: simulators, parallel software development environments, NoC debuggers. An important gap is observed concerning a complete NoC-based MPSoC: tools to inspect the traffic exchanged between processing elements in a higher abstraction level, and not simply as raw data. This is the goal of the paper: propose a new class of debugging tools, able to trace the messages exchanged between PEs, enabling debugging at the protocol level. Examples of protocols include communication between tasks, mapping heuristics, monitoring schemes for QoS, among others. The paper presents the proposed debug framework, as well as a task migration protocol as case study.