With the end of Moore's Law, database architects are turning to hardware accelerators to offload computationally intensive tasks from the CPU. In this paper, we show that accelerators can facilitate far more than just computation: they enable algorithms and data structures that lavishly expand computation in order to optimize for disparate cost metrics. We introduce the Pliops Extreme Data Processor (XDP), a novel storage engine implemented from the ground up using customized hardware. At its core, XDP consists of an accelerated hash table to index the data in storage using less memory and fewer storage accesses for queries than the best alternative. XDP also employs an accelerated compressor, a capacitor, and a lock-free RAID sub-system to minimize storage space and recovery time while minimizing performance penalties. As a result, XDP overcomes cost contentions that have so far been inescapable.

An innovative algorithm is introduced for cycle slip detection and correction in communication systems that employ APSK modulation. The algorithm is well suited for carrier phase synchronizers that are based on phase locked loops, and it achieves significant improvement in BER performance without compromising spectral efficiency. A systematic approach for the selection of all main algorithm parameters is detailed. In particular, the 16-APSK scheme, (recommended in the DVB-S2 standard) is analyzed by assuming an AWGN channel, and simulation results in the presence of various channel impairments are presented. The results establish the superiority of the proposed algorithm over other known cycle slip handling techniques for PLL synchronization. Integration with state-of-the-art iterative synchronization is also considered.